One of the reasons I love being a part of the semiconductor industry is its rapid rate of change. In this column and the next, I'll share with you a preview of design implications arising from the soon-to-be-released 1999 International Technology Roadmap for Semiconductors. The ITRS has become the worldwide navigational guide for the semiconductor industry, synthesizing the efforts of many hundreds of people. Since 1996, I've been privileged to join more than 30 other experts in the field of design to help coauthor the design and system-on-a-chip chapters. Perhaps this text will merely serve to confirm what you already know, or possibly begin an active transition towards some of the key trends coming in design.

Semiconductor technology advancement has been truly astounding a 58 percent annual improvement in usable transistors and a greater than 20 percent annual decrease in costs. It has fueled our economic growth for the last decade of this century, and likely the next decade to come. This growth stems largely from the consumerization of electronics, which has created entirely new markets as functionality and affordability continue to march forward. Furthermore, the trendy whims of consumers as well as the intense competition have accelerated the priority on time to market for nearly all product categories.

It's a well-established fact that our ability to create new designs hasn't kept up with our ability to manufacture them in silicon. This fact is the founding tenet of the need for design reuse, and looking ahead, we will find that it's also one factor in the shift towards greater software flexibility. As we look ahead to very fine process geometries, the challenges that we face are equally astounding. We will be dealing with metal "wires" less than 50 atoms wide, routed in three-dimensional silicon cubes eight or nine layers deep. This combination will create vias so long and narrow that even scanning electron microscopes won't produce the depth of field required to catch tiny errant particles. Welcome to the world of particle physics.

Moore's suggestion

This industry has followed the density curve of Gordon Moore for so long that it has gone beyond mere conventional wisdom: it has become gospel, a sort of self-fulfilling prophecy. For years, I have referred to "Moore's Law" as "Moore's Suggestion," because our ability to sustain that rate depends upon the power of suggestion, not upon any fundamental laws. We invest at that rate necessary to fulfill our prophecy, because we believe the investment will always provide much greater returns. The laws of physics, however, are even more compelling. As investment costs rise, it's left to design to find better ways to use these investments to increase value, and thus revenue. The rising costs of high-tech fabs are quickly becoming a rich man's game, and only the companies that truly understand the increasingly critical role of design will be able to effectively compete in the coming era.

So just how big and fast will these chips be? Within the ASIC category, we're already beginning to see the changeover from the "parts is parts" mentality to a high-performance system application focus. Thus the roadmap predicts that ASIC density, size, and clock rates will track very close to those of microprocessors while still maintaining a time to market priority!

Roadmap grand challenges

The design chapter of the ITRS lays out the grand challenges in terms of five dimensions of complexity. Silicon complexity, which enables the other four, not only includes the pervasive interconnect challenge, but also places higher priority on power management, signal integrity and reliability, voltage scaling, and new logic families. Even with copper and low-K dielectrics, the combination of the multi-GHz clock frequencies and the extremely long global interconnect will force new on-chip communication methods. We must recognize that systems on silicon are, in fact, systems in their own right, and consist of subsystems. While each subsystem may operate synchronously, global interconnect will require that these subsystems communicate asynchronously ("locally synchronous, globally asynchronous"). Just as in today's large systems, most asynchronous communication will occur through protocols and buses. The next-generation EDA tools must intrinsically comprehend such paradigm shifts in design architecture. For design and EDA, such issues may seem miles apart from the more interesting concerns of high-level functional complexity. Yet these two aspects are inexorably intertwined as we delve below 100 nanometers.

The second grand challenge is system complexity. In this context, we can't overestimate the role of embedded software as an essential design problem. Yet the concept of heterogeneity will extend far beyond digital hardware and software. The integration trends for silicon are already moving critical analog and mixed-signal functions on chip. With the popularity of wireless devices sure to increase in the coming decade, the integration of RF functions can't be too far behind. Even within the digital domain, the gap is growing between the application-level semantics for system-level representations and our present means of describing them in EDA tool flows. The diversity of design styles will also include electro-optical and micro-mechanical (MEMS) systems. The challenge lies in how to represent such diverse functionality across multiple semantic domains in an integrated fashion that can be verified prior to actual silicon.

Verification and analysis complexity presents the third grand challenge. As we increase the number of views into a design that must be analyzed, we find an increasing array of specific algorithms that must communicate with each other and the designer as the design evolves. Designers will need new methodologies to help the scaling of this process as design sizes approach 50 million gates (particularly true for core-based designs). Design architecture, partitioning, and modeling must all adjust for the practical realities of verifying the design within shrinking cycle times.

The fourth grand challenge is design procedure complexity. Designers need a convergent and predictable design process that incorporates all of the system and silicon complexities. Because such a wide and disparate array of technical expertise is required, we will increasingly find design teams assembled in a distributed fashion across geographically dispersed regions.

The fifth grand challenge is test complexity. Designers rarely get excited about inserting design for test, but there will soon be no alternative to producing real products for a real market. Even assuming unacceptably costly testers (exceeding $20 million), physics-based interconnect limits will virtually prohibit at-speed testing. Furthermore, the integration of analog and RF functionality will accelerate the need for on-chip built-in self-test (BIST).

More data, please

The ITRS is filled with tables that make projections for future silicon capabilities, laying the foundation for some of the design-related implications required to keep pace. It should be noted that, while all future projections have a distinct likelihood of being wrong, the history of the ITRS roadmap shows that its targets have almost always been exceeded in practice. With that in mind, let's make a few simple comparisons for the ASIC category between today (the end of 1999) and the year 2005 (see the table).

Clearly, over the next five years we will witness several key paradigm shifts as the industry attempts to keep this pace, especially in terms of ASIC characteristics. If we assume a 50 percent logic density for auto layout and six transistors per gate, then over the course of the next five years we'll see ASIC gate counts explode from 13.3 million to a whopping 88 million. Furthermore, localized digital clock frequencies will hit 3.5 GHz, while global interconnect must run at nearly 1 GHz. At the same time, high-performance devices will be dissipating 160 watts, yet advanced low-power design techniques must maintain an average power consumption of just 2.4 watts. Since projected design cycles remain constant at 12 months, the required ASIC design productivity jumps five times beyond today's capabilities. This pace amounts to a doubling of design productivity every year between now and 2005.

These developments imply some serious change.

Historically, the greatest improvement in design productivity has always occurred through the raising of abstraction levels. The ability to design and analyze at higher abstraction levels will be key to this design productivity requirement. In a sense, design reuse through IP megamodules and blocks is another form of designing at higher abstraction. The trick comes when we combine top-down and bottom-up design constraints into a consistent methodology.

The need to find solutions upstream isn't unique to design. Many of the challenges in test, interconnect, assembly and packaging, and lithography can't be addressed without changes in how we do design up front. For example, fundamental laws of physics will prohibit testers from keeping pace with on-chip clock speeds; at-speed testing must be replaced with on-chip BIST. Similarly, the increasing sequential depth and breadth of logic would eventually require over one billion test vectors behind every signal pin, forcing testers to run for hours or days. Once again, the only feasible alternative is BIST, which becomes even more challenging as designers integrate analog and mixed-signal functions with digital logic.

The challenges of routing long interconnect and managing critical timing paths may force the use of more complex 3-D structures as well as SOI (silicon on insulator) to reduce capacitive effects. The potential introduction of gate-stacking technology could open the door to new design interconnect architectures, such as systolic arrays. In another example, increasingly wide off-chip I/O must be integrated away to address packaging technology limits. Thus, "system on a chip" may soon share headlines with "system in a package," as multiple dice share a common substrate and package to handle the coming design trends.

The great walls

I see two fundamental walls ahead. A technology wall of "no known solutions" certainly looms around the 50 nanometer node. Yet, I believe that an economic wall may loom much earlier, perhaps around the 100 nanometer process node. That's the point at which the cost of investment in the level of return can no longer be justified in the general case. At that point, the design community will feel even greater pressure to find new ways to improve efficiencies and levels of capability to sustain the healthy revenue growth we have enjoyed in recent times.

I welcome your feedback on these projections, and encourage you to check out the 1999 ITRS at www.itrs.net/ntrs/pubIntrs.nsf. In next month's column, I will share my perspectives on the impact of these changes to the EDA industry.