mixed-signal

A PC-based Design Flow for Advanced Imaging ICs Engineers develop full-custom mixed-signal ICs for electro-optical imaging systems using PCs and a mix of capable EDA tools. by James T. Woolaway

Every day we rely on electronic imaging to reveal to us what we can't ordinarily see--from TV images beamed around the globe to infrared images of primordial galaxies near the edge of the universe. The advanced electro-optical imaging systems that deliver the images present opportunities as well as challenges for the designers of their ICs. Imaging systems operate in the complete range of the electromagnetic spectrum, from microwave to infrared to X-ray, and they often must endure extreme environmental conditions. Moreover, their performance specifications typically must comply with very stringent standards. Noise, sensitivity, dynamic range, power dissipation, and speed are crucial considerations, as are resolution, size, and functional flexibility.

Figure 1	ROIC design process
The design process for the readout ICs begins with general concept development and progresses through detailed analog/digital design, IC layout, and DRC and LVS verification.

At Indigo Systems, we design high-performance mixed-signal chips for imaging systems used in military, aerospace, scientific, medical, and commercial applications and have thus dealt with the challenges first-hand. Through our experience developing numerous mixed-signal ICs--called readout ICs (ROICs)--for the various electro-optical application areas, we've devised a highly productive design methodology for generating mixed-signal designs with such demanding constraints.

Even though we employ a full-custom design approach, the methodology enables us to develop designs of up to 16 million transistors in about three months. Our Windows-based EDA tools powerfully facilitate our design flow, offering the performance we need without burdening us with the added cost and unnecessary complexity of a comparable Unix-based tool suite. During concept development, the iterative combination of OrCAD's Schematics, Pspice, and Probe helps us construct optimal subcircuits and run first-order simulations on them using extensive, editable libraries. This same iterative sequence of tools is also fundamental to our detailed analog and digital design phase, during which we create netlists and carry out various performance-level verification tasks. Moreover, the Windows environment of our EDA tools makes them fully compatible with a full suite of other Windows-based software for presentation, analysis, IC design, and logic simulation, which allows us to readily perform external analysis and create support documentation.

Electro-optical demands

Transposing an image onto an electronically malleable form is no easy task. The sensor array transforms the intensity variations across the image into a corresponding spatial map of analog electronic signals, with each detector uniquely generating electrons according to the number of photons it absorbs. The difficulty comes in collecting the vast number of discrete analog signals from the detector array--which can contain a million or more sensors--and moving them to the rest of the imaging system in an intelligible format and with the highest fidelity. Further complicating matters is the fact that different sensors have different operating parameters. X-ray detectors, for example, work differently from IR detectors. Even a single type of detector can behave differently under different circumstances.

Figure 2	Functional block diagram of the ISC9705
The 3203256-pixel ISC9705 ROIC is a complex chip combining logic and mixed-signal components that must interact as efficiently and noiselessly as possible.

Our ROICs sort out such complexities to define the critical link between the detector array and the final image. The devices take the signals from the detectors and reduce them to a handful of high-speed analog or digital data streams. The sensor array and ROIC are united into a single hybrid unit using such micro-interconnect technology as indium bump bonding; therefore each unit cell of the ROIC is constrained to the same real estate subtended by the sensor it controls. If, for instance, the detector array has a 30-µm pitch, each unit cell of the ROIC must match that pitch.

Once hybridized with the sensor array, each unit cell of the ROIC can control its companion detector in several ways. Typical control features include detector biasing, input signal integration, sample and hold, gain control, electronic shuttering, antiblooming, and signal multiplexing. The ROIC must also incorporate certain chip-wide functions, such as column amplification, signal skimming, signal multiplexing, image transposition and windowing, temperature sensing, A/D conversion, clocking, and logic control.

The integration of many mixed-signal functions onto a single ROIC, along with the physical constraints imposed by the sensor array, creates formidable design challenges. Many of the chip's functions--sampling functions, input amplifiers, output drivers, and bias and clock generators--are mixed-signal components. Collecting and processing photons is inherently noisy; 10,000 integrated photons represents about 100 carriers of RMS noise. Since the ROIC must contain fewer than 100 carriers of RMS noise to accurately produce the analog signals, noise control requires considerable attention.

Critical decisions

Thus constrained, fundamental aspects of our design methodology emerge. Ensuring optimal low-noise performance of analog signals requires painstaking attention to the placement and operation of every circuit and every transistor in our ROICs. Hence, we handcraft each ROIC layout--even those large-format designs containing a million or more transistors.

Practical considerations dictate our selection of design platform. We could use Unix-based software for our design procedures, but much of what you pay for with those tools is higher-level design capabilities for automated layout and synthesis. In our world of full-custom design, where we draw every transistor, it's not uncommon to spend a week or two crafting the unit cell for one of our chips. So it makes less sense to pay for automated design capabilities that we don't need and that are more difficult to use. Windows-based EDA tools, in contrast, cost less, are relatively easy to use, and can assist the kind of design and analysis we need. In addition, they are thoroughly compatible with the vast library of existing Windows-based software for word processing, analysis, and presentation, as well as countless other applications.

Thus we develop our designs on PCs running under Windows NT. Specifically, we utilize Micron PCs with dual Pentium II processors, Ultra Wide SCSI disks (4.5 Gbytes of storage capacity), and 128 Mbytes of RAM. That configuration provides adequate computing power for all of our design processes, though several of our engineers are outfitted with two computers that can perform long simulation and layout-versus-schematic runs in parallel. PC-based EDA software from OrCAD, SimuCAD, and IC Editors completes the design station.

A three-phase design methodology

We execute the design process in three major phases: conceptual design, detailed design, and layout. We begin the process by developing an overall concept of chip function and architecture on which we carry out first-order analog simulations and analysis of noise, power, and real estate (see Figure 1). Once we establish a workable general concept and IC architecture, we move to the detailed phase of analog and digital design, during which we create circuit schematics on which we run comprehensive simulations and analyses and generate netlists for each circuit that feeds into our layout tool set. In the final design phases, we do full-custom IC layout and routing, design rule checking, and LVS verification.

Figure 3	Levels of Pspice
The differential amplifier and multiplexer switches of the output multiplexer amp appear in Pspice at two different levels in the schematic hierarchy of the ISC9705 design.

One of Indigo's most popular off-the-shelf ROICs--the ISC9705--serves as a good case study for our design process. The ISC9705 is an advanced, midformat (320 x 256 pixels) ROIC designed for a variety of p-on-n photovoltaic detector arrays for visible and IR applications. The chip supports many important imaging functions, such as snapshot integration, integrate-while-read, integrate-then-read, dynamic image transposition and windowing, and temperature sensing, as well as multiple output configurations. To support as many applications as possible within the IR waveband, digital programmability via a serial control register allows the user to choose among several output modes: windowing, skimming, and gain. The chip is fabricated on 5- or 8-inch wafers using a 0.6-µm, single-poly, double-metal mixed-signal process.

We began the conceptual development of the ROIC with a survey of various visible and IR applications for p-on-n detectors, because we wanted the ISC9705 to meet the needs of a variety of users. With diverse applications in mind, we first looked at the theoretical performance that we needed to achieve and then tried to come up with a viable circuit concept. We looked at such things as circuit traits, theoretical noise, power dissipation, and the real estate requirements for different manufacturing technologies. From the analysis, we put together a functional block diagram (see Figure 2).

Once we defined how we wanted the chip to work, we designed each subcircuit. For example, we specified what topology, components, and biasing to use. We then captured the design using OrCAD Schematics (formerly Microsim Schematics) and customized device libraries for the IC's mixed-signal process.

Figure 4	Tracking irregularities in the mux amp
(a) (b) Goal-function results of parametric simulations performed on an output multiplexer amp imply that its response is linear (a), but an Excel plot of the best-line fit proves otherwise (b).

After we generated the schematic, we ran simulations on it with Pspice. Simulation can be a time-consuming chore, especially on complicated circuits containing large numbers of devices. It's not uncommon for us to run simulations on circuits containing more than 1,000 devices; beyond that, the performance required of the ROICs forces us to conduct many different kinds of simulations on each circuit. Since long simulations hinder design productivity, it's very important that each simulation converge quickly. Generally we've found that the convergence algorithms of Pspice allow simulations to converge quickly, which is a significant advantage.

When the Pspice simulation was complete, we used OrCAD Probe to analyze the results. The tool helped us look at any of the device currents and node voltages in the circuit for a specific analysis. For example, we could run a transient analysis to examine the time-domain characteristics of the node voltages and currents throughout a circuit. Probe can graphically display simulation results such as multiple-current or -voltage traces. It also supports several other mathematical functions, such as integration and differentiation. Those functions helped us to determine whether the circuit was performing correctly.

If a circuit didn't meet the desired performance requirements, we modified its design by making changes to the schematic and then ran a new simulation, using Probe to examine the new results. The iteration and reiteration among the three design tools--OrCAD Schematics, Pspice, and Probe--helped us quickly home in on an optimal design, which was particularly important during the conceptual design phase, when we were exploring new architectures and new types of circuits. We designed and optimized each circuit of the ISC9705 in that way, schematic by schematic, until every subschematic of the hierarchical design was performing to our specifications. Finalizing the design involved integrating each subschematic into a single hierarchical "golden schematic."

In with the output

The chip's output multiplexer amplifier typifies one such subschematic. As portrayed by the schematic capture tool of Pspice (see Figure 3), it consists of eight transmission gates (symbolized as Tgate) that allow a single differential amplifier (OUTAMP) to connect to eight different bus lines (OBUS0 through OBUS7). Also coming in are eight lines from the multiplexer bus; eight logic control lines and their complements; and a series of supplies for substrate potential and negative, positive, and reference bias.

The subschematic for the OUTAMP symbol (shown in the blowup) is one level down in the design hierarchy. The subschematic illustrates how we used Pspice to build up symbols and hierarchies that represent different sections of the chip at different levels of the design. First we designed and optimized the actual amplifier using the iterative process described above, then we symbolized it as OUTAMP and began to analyze it in three contexts: the multiplexer, the signal chain, and the ROIC and system interface.

Pspice offers two very useful types of diagnostics--goal functions and parametric analysis--that we employed at that stage of the design. The goal-function diagnostic allowed us to analyze a circuit for a particular goal function such as rise time, fall time, or circuit bandwidth; parametric analysis let us vary component values over multiple simulation runs and view the results as a set of curves. Together, the two Pspice tools provided a powerful means to verify the performance specifications of our design. In the output multiplexer amp, for instance, we used such a method to analyze the effects of an increasing signal level for a single pixel through the multiplexing chain. In that application, we accessed a y-at-x goal function that outputs the y value for a parametric analysis at a particular x value, which in that case was time (see Figure 4). The response over a dynamic range of 0.5 to 3.5 V appeared to be linear. However, after pasting the goal-function results into Microsoft Excel and analyzing the percentage error against the best-line fit, we noticed a small but unacceptable deviation from a straight line.

Figure 5	Handcrafted layout of the mux amp
A detail from the layout of the select control logic (top) and the multiplexer bus and the transmission gates (bottom) typifies an Indigo Systems ROIC cell layout. A custom layout technique evident here is the use of interdigitated metal 2 ground lines (bottom) that shield adjacent bus lines from one another.

By simply copying information from Probe onto the clipboard and then pasting it into Excel, we could perform mathematical analysis that otherwise wouldn't have been possible. Similarly, we could easily transfer information into presentations, user manuals, and reports.

The output amplifier is one of some 100 schematics used to build the chip, each instantiated on as many as 10 levels of hierarchy. We used the schematics to build a golden schematic, then the multiple-views feature of Pspice to allow the golden schematic to work with other tools. That capability enabled us to translate a netlist of the same schematic into different tools and simulation environments such as SimuCAD's Silos-III--which we use for full-chip logic simulation--and our IC layout, DRC, and LVS tools from IC Editors, which were used in the final phase of our overall design process. Despite some duplicate effort required initially to generate technology files for each environment, dealing with the multiple environments had a negligible impact on productivity. Our hardware-software combination handled with relative ease the pasting of anything from a clipboard of a 10-kbyte file into Excel to the transference of a 1-Mbyte netlist from OrCAD.

Next, we moved to the final phases of the design process. Taking schematics and netlists from the OrCAD environment, we built the layout using IC Editors' layout editor. The fact that our design required handcrafting made layout a significant aspect of our overall design flow. For example, the demanding physical constraints imposed on the unit cells made layout of the cells a difficult and time-consuming task. It wasn't uncommon to spend a week or two crafting just one unit cell. Using the tool's command file capability, we saved design time on repetitive tasks by writing programs that generated command files. The command files, in effect, automatically "synthesized" cells for us so that we didn't need to re-create common structures from scratch. Wherever possible we endeavored to save effort and real estate by mirroring about symmetry to share common elements between cells and also to share functions among cells. A sample layout--the output amplifier--appears in Figure 5.

The last stage

We completed the design process with DRC, netlist extraction, and LVS verification. Once we finished the layout of the cells and chip hierarchy, we used IC Editors' DRC tool to verify that the layout met our process design rules. The tool identified an error by highlighting the errant geometry, which we rectified by determining which rule had been violated and then adjusting the layout. We then used IC Editors' netlist extraction and LVS tools to verify that the layout accurately reflected the schematics and netlists from the OrCAD environment of our detailed design phase. To ensure that the next phase ran as smoothly as possible, we defined and adhered to naming conventions that enforced consistency between our back-end and front-end circuit representations.

The entire ROIC design process takes about three months, and our team of 10 designers undertakes about one new design per month. The first two design phases--conceptual and detailed design--each take about a month to complete. The layout phase takes about six weeks, but because some layout processes can occur in parallel with detailed design, the layout phase adds only four weeks to our overall design schedule. In order to maximize productivity, we employ data management techniques such as batch processing of lengthy LVS and simulation runs. As mentioned above, we also provide two computers to engineers engaged in computationally intensive tasks. The PCs we use, configured as they are, deliver performance comparable to workstations.

We've designed chips containing over 16 million transistors using our tools, and though every tool set has its advantages and disadvantages, PC-based tools certainly have a place in the world of full-custom IC design.

James T. Woolaway is a cofounder and vice president of engineering at Indigo Systems Corp., Santa Barbara, Calif. Prior to Indigo's launch three years ago, he served as a senior principal engineer at the Santa Barbara Research Center. He has worked for 18 years in the electro-optical imaging industry.

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integrated system design  February 1999