asic design

Understanding Encroaching Parasitics Can Help to Ensure Signal Quality Careful interconnect analysis is becoming more important in the designer's quest to satisfy timing and signal quality requirements of deep-submicron processes. by Jon Levi

The need for better analysis of interconnect in the deep-submicron realm has received a great deal of press in the recent past. Deep-submicron processes, of course, allow higher levels of integration and functionality--but at the cost of greater complexity and the need for greater accuracy in simulation to ensure timing. Unfortunately, along with increased levels of device integration come higher on-chip speeds and less margin for error in all of the timing parameters.

The smaller process geometries continue to shrink minimally loaded gate delays to less than 100 ps in a typical 0.25-µm process, with rise and fall times on the same order of magnitude. In the near future, process generations will sport even lower delays, while offering the capability for designs exceeding 10 million gates. The heightened design and process complexity, however, creates a deep-submicron design and analysis problem: The interconnect now contributes the majority of the delays in a circuit. The latest SIA roadmap charts a disturbing trend for future process geometries. As they move below 0.35 µm, not only does the interconnect increasingly determine length of delay, but the total delay increases. The interconnect is now the main factor in determining delay and power consumption, which makes accurate timing analysis and back annotation for physical verification very difficult but absolutely necessary in today's designs.

Figure 1	Metal trace configuration
The metal trace configuration for this example shows the center trace "T" surrounded by trace 1 on the left and trace 2 on the right.

Typical estimates for percentage of delay in a deep-submicron design attributed to the interconnect lie between 60 and 90 percent. In addition, the bulk of the delay no longer stems from the capacitance from the line to substrate--a grounded capacitor--but from the sidewall parasitics--a floating capacitor. The increasing amount of interconnect (10 million nets ¥ 100-µm average interconnect length = 1,000 meters total length), coupled with the changes in the composition of the interconnect loading, contribute the bulk of the loading effects seen in designs. Not only is the total length of the interconnect increasing, but the distribution of lengths is also changing. The average and longest lines are lengthening to the point where the longest lines--as much as 2 cm total--are longer than the outside dimensions of the chip, thereby exacerbating the problems in the interconnect. Unfortunately, the longest lines are usually also the most heavily loaded lines, making a difficult analysis case much worse.

The combination of faster edges and longer interconnect loading creates various problems. Clearly, increased interconnect loading has been shown to interfere with timing, but other effects further deteriorate timing. Some of the effects caused by loading, for example, change the propagation delays through the gates. Still other characteristics affect the signal quality.

Since interconnect delays need much more detailed analysis, the design flow must add more tools and processing steps. For many circuits, the parasitic extraction must use full 3D methods to achieve appropriate accuracy, because of the increased fringing and cross-coupling capacitance and increased resistance in the wiring. Unfortunately, the extra loading can wreak havoc on a circuit's performance.

Parasitic loading
Additionally, changes in numbers of parasitics have two main effects: increased signal loading and decreased signal propagation velocity. First, more parasitics intensify the loading on each gate output. The extra loading increases signal rise and fall times, which in turn augment the gate delay for downstream gates by lengthening the time for the signal to reach the switching thresholds--a phenomenon caused by the limited drive current available to charge the capacitive loads. The necessary current is represented by the formula (I = C ¥ (dv/dt)), where C is the load capacitance composed of the next stage input capacitance and the lumped interconnect capacitance. The formula indicates that smaller transistors may not be able to drive the larger loads at full speed. For example, the current required to drive the next-stage input capacitance is (Iª10 fF ¥ 2 V/100 ps = 0.2 mA).

Figure 2	Out of phase
The in-phase (yellow) and out-of-phase (blue) signals in adjacent conductors can greatly disrupt the timing of the conductor under analysis. (The original trace is in purple.)

Because the current and the signal swing are constant for a given device size, any increase in C causes a corresponding decrease in the transition times. The next stage doesn't switch until the input voltage exceeds the transistor threshold, and the slower output ramp from the driving stage takes longer to reach the switching threshold. In addition, the slower ramp rate also means that the transistor doesn't switch quickly from on to off (or vice versa), but instead makes a slower transition through the linear conduction region, further retarding the signal propagation through the stage.

Second, the simulation for the interconnect as a transmission line shows that the signal propagation velocity decreases as loading increases. The decrease in velocity adds more delays to the signal path. The very fast signals, in which rise and fall times for unloaded gates are less than 100 ps, force the designer to move from the simple digital approximations of clock-synchronous 1s and 0s to analyses of RF-type effects and analog signal interaction.

The most prominent results of all this additional gate loading include problems not only with the timing but also with signal integrity, electromagnetic interference (EMI), metal migration or reliability, and power or thermal management. The actual signals flying around on the chip never look like the nice waveform displays in simulation. Loading effects and other signal integrity issues require understanding of signal characteristics to accurately model the delays in a design.

Signal analysis in practice
The theory and accumulated measurements of high-speed signals show that when the propagation delays are greater than twice the fastest edge, the interconnect needs to be analyzed as a (lossy) transmission line. Signals within a lossy transmission line are subject to various types of degradation, such as constructive and destructive reflections that cause ringing, overshoot, undershoot, and glitches. The signals also exhibit increases in rise and fall times that change waveforms and exacerbate the difficulty in determining the logic thresholds. The reduction in supply voltages and corresponding decreases in signal swing reduce noise immunity, making circuits more susceptible to aberrations in signal quality. With unloaded gate rise and fall times below 100 ps, designers should analyze any delays exceeding 200 ps by modeling the net elements as a transmission line and not just as lumped capacitance and resistance elements.

A relatively generic set of rules describes the physical layout of a very simplified example (see Figure 1), which shows the results of the interconnect for a small section of a memory in a 0.5-µm process. The analysis scales for smaller and faster devices, so a smaller topology gate exhibits roughly the same loading. The smaller metal pitch increases resistance but decreases substrate capacitance by the same ratio. The sidewall fringe capacitance contributes much of the increase. A cross-section view of the metal for the interconnect reveals the three metals, which consist of parallel traces of 0.5-µm square cross-section aluminum on 1.0-µm centers, with 1-µm interlayer dielectric. All analyses are relative to the center trace for the simplified set of interconnects. The line characteristics are analyzed for three different line lengths--100 µm, 1 mm, and 1 cm--including a signal source with 200-ps rise and fall times, a 2-ns clock period, and a 1,000-driver impedance. The circuits are considered to be open terminations and the subcircuits for the interconnect include both capacitive and inductive (C and L) coupling effects.

The table indicates the relative magnitudes of the interconnect's extracted parasitics in this example. As the device and process dimensions continue to shrink, the value of all of the parasitics increases, magnifying the effects of the interconnect on IC performance. Since the simplified example assumes a homogenous environment for the interconnect with no discontinuities caused by vias or metal size changes, it isn't really valid for the longer traces, which would yield even worse results than shown here.

Logically, the worst-case capacitive load occurs when the two outer traces are out of phase with the center conductor. This case doubles the effective capacitive loading, because the driver must completely charge and discharge the parasitic capacitances to the maximum voltage possible (see Figure 2). The waveforms in the figure show the effect of the adjacent signal lines on the center trace for a 1-mm-long trace. The yellow trace shows the minimal distortion to the output signal when the lines are driven in phase. The blue trace shows the level of distortion and signal degradation when the adjacent signals are out of phase. Note that the mismatched phase delays the signal by almost 200 ps and increases the rise and fall times to almost 1 ns.

Figure 3	Spice block model
The configuration of the source and load impedances is coupled with the block model for the interconnect.

The maximum capacitance is thus equal to the line-to-substrate capacitance plus each of the sidewall capacitances (Cmax = C11 + C12 + C13 or 0.19 fF/µm = 0.07 fF/µm + 0.06 fF/µm + 0.06 fF/µm). Shown is the configuration for a Spice block model including the driving and termination resistances, along with the different length models for the interconnect (see Figure 3).

Figure 4	The longer the trace....
Trace length affects signals by degrading all signal parameters, especially timing and amplitude. The longest trace (green) fails to produce a signal sufficient to switch before the next clock edge.

The length of the traces exerts a considerable effect on the signals (see Figure 4). Note that the red line for the 100-µm trace length shows minimal distortion, with only a slight increase in delay and rise and fall times. The blue line, representing a 1-mm line length, shows the delays and increases in rise and fall times noted previously. Finally, the green line shows the effect of a 1-cm trace with effective rise and fall times exceeding the clock cycle. The intrinsic interconnect RC rise and fall times are expressed as (1.1 ¥ Rl ¥ Cmax = 1.1 ¥ 0.11/µm ¥ 0.19 fF/µm) or 0.023 fsec/µm2.

Total effective rise time is evaluated as the square root of the sum of the squares [Tr¢ = ÷(trline2 + trgate2)]. The interconnect delays are calculated as a function of a 20-element lossy transmission line. The approximation that capacitance and resistance are linear functions of total length is appropriate only for low-rate transitions on short lines and for evaluating the changes in rise and fall times caused by the interconnect loading. The effects of the increased output transition times are longer delays in the interconnect and slower switching times in the downstream gates.

The gate delays increase because of the slower charging of the gate capacitances. When the transistor is modeled as a voltage-controlled voltage source, a slow ramp signal propagates delays because the output doesn't start to change until the input signal exceeds the transistor's threshold value. The output can change only at a maximum rate equal to the input signal when the P-N pair lie in the linear range between logic levels--unless the circuit is designed with some type of feedback that will increase transition rates when the signals pass logic thresholds.

The net effect of all the processing changes is an incremental slowdown of all signal movements. It's exacerbated by the increasing signal speeds, wider buses, and increased path lengths--all of which make timing convergence much more difficult to achieve. In fact, without some type of floorplanning and critical-path parasitic extraction and analysis, designs are fated to suffer the continuing consequences of chaotic layouts and excessive, time-consuming iterations to meet both timing constraints and specifications.

Interconnect models are becoming more sophisticated and accurate, reflecting the increased attention and understanding that this critical aspect of the post-layout analysis is receiving. The extraction and modeling of interconnects has progressed from models of average-length lumped loads to detailed, measured values of primitive interconnect elements. So, although the models have improved, the analysis tools have improved as well. The engineer doesn't have to build up a netlist of Rs and Cs, but can simply describe the physical characteristics of the interconnect--and let the program develop the detailed models.

Thanks to Eric Bogatin of Ansoft Corp. (Santa Clara, Calif.) for preparing the data and running the simulations for this article.

To voice an opinion on this or any Integrated System Design article, please email your message to jeff@isdmag.com.

integrated system design  June 1999