As designs become larger and more complex, the need for reusable blocks of intellectual property (IP) increases. The use of IP helps accelerate time to market, and allows the designer to focus on the unique, high-value-added portions of the system. However, using third-party IP can be risky. Fortunately, the right design flow with parameterizable, reusable IP that can be evaluated before purchase can reduce risk and accelerate the design process. By using such a design flow, a design team can implement a design by downloading the IP via the Internet, parameterizing it, and evaluating it fully integrated within the system all prior to licensing the IP core.

Figure 1 - Hypothetical modulator system

A typical DSP modulator might combine an outer encoding layer, and inner coding layer, and FIR filters, sending its output through a digital-to-analog converter (DAC).

We used this design flow to implement a finite impulse response (FIR) digital filter as a part of a transmission impairment measurement set (TIMS) module line card used in the Hewlett-Packard service advisor test tablet, a hand-held tablet that enables the field testing of communications equipment such as ATM, SONET, and xDSL.

Let the FIR fly

Many digital systems use signal filtering to remove unwanted noise, attenuate or boost certain frequency components, provide spectral shaping, or to perform signal detection and analysis (see Figure 1). Two types of filters that accomplish these functions are finite impulse response (FIR) filters and infinite impulse response (IIR) filters. FIR filters serve in systems that require exactly linear phase response, which, except in some very specific cases, IIR filters can't achieve. In contrast to IIR filters, FIR filters also benefit from an inherently stable frequency response. Yet, it is important to consider the potential cost of additional hardware versus an IIR filter with an equivalent frequency response. IIR filters, which are inherently unstable, can work in systems that tolerate their intrinsic phase distortion.

The structure of a FIR filter uses a weighted, tapped delay line (see Figure 2). The filter design process involves identifying coefficients that match the frequency response specified in the system. The coefficients determine the response of the filter. Many sets of coefficients possess special properties, such as symmetry, that can significantly decrease the size of the filter.

Figure 2 - Basic FIR filter

The designer can change which signal frequency passes through a FIR filter by changing the coefficient values.

The first step in designing a FIR filter is to determine the desired frequency response, sample rate, and precision, based upon system requirements. Next comes the calculation of the coefficients, which, when implemented in a FIR filter, uniquely determine the filter's characteristics.

The calculation of coefficients takes four steps. First, specify the desired frequency response. Second, specify the implementation conditions to enable the realization of the filter in hardware. For example, the filter must contain a finite number of taps, limited precision (data and coefficient word width), and real (as opposed to complex) coefficients. Third, take the inverse discrete Fourier transform (IDFT) to get the filter's impulse response. The impulse response values are the FIR filter's coefficients. Last, weight the coefficients by multiplying the impulse response by a "windowing" function to reduce distortion (side lobes, for example) caused by the finite duration of the impulse response. Following this procedure, implement the filter and verify that the realized frequency response is as desired.

Interpolation and decimation are two of the operations commonly employed in systems that use FIR filters. Interpolation adds points to the actual data samples to increase the apparent sample rate. Decimation removes unneeded sampled data points.

The system described here requires a decimating low-pass FIR filter. Decimation allows the designer to use a simpler analog anti-aliasing low-pass filter than would be otherwise required, by increasing the rate at which the data is sampled. An anti-aliasing filter accords with Nyquist's sampling theorem, which states that the data sampling rate must be at least twice that of the highest frequency component in the input signal to avoid aliasing a phenomenon that causes severe distortion by shifting high-frequency information to lower frequencies. The decimation process allows an increase in the sample rate and then removes these excess samples to produce a rate consistent with the needs of the system.

The alternative architectures that can implement FIR filters are all based upon two basic structures parallel and serial. A parallel implementation calculates the filter output in a single clock cycle. The width of each storage element in a tapped delay line equals the data width, WDATA. There are N WDATA-wide storage elements, where N is the number of taps. Parallel filters provide the highest performance but consume the most area, because of the need for N large multipliers, where each multiplier is WDATA by WCOEFF.

A serial implementation is smaller and slower than a parallel FIR filter. It requires the same number of storage elements and multipliers, but the size of each multiplier is only 1 bit by WCOEFF. It takes WDATA clock cycles to produce each output.

System overview

We implemented the FIR filter used in this design in an Altera FLEX 10K100 356-pin programmable logic device (PLD) in a ball-grid array (BGA) package. The PLD interfaces with an on-board DSP processor, an analog/digital converter, and the system processor. The TIMS module in the Service Advisor Test Tablet uses various sample rates with the appropriate analog anti-aliasing filters to accurately test and analyze frequencies ranging from 50 Hz to 2 MHz. The PLD is the heart of the measurement system, and serves to generate the sample clocks, select the proper analog filters, and perform a wide variety of other tasks.

We added new functionality to the Service Advisor Test Tablet that required the DSP in the TIMS module to work at a sample rate eight times slower than the slowest available sample rate clock. We needed the ability to use our existing analog anti-aliasing filters, since adding a new analog filter would increase time-to-market and raise the risk inherent in a new PC board spin. Unfortunately, it wasn't feasible for us to use the DSP to implement the filter because it didn't have the necessary performance bandwidth. Implementing a low-pass decimating FIR filter in the system PLD was the best way to preserve our existing analog filters.

It's useful to note that DSPs contain a limited number of multiplier-accumulator (MAC) units, which require many clock cycles to compute each output value. This limitation slows the overall performance of the filter. By contrast, the fully parallel, pipelined FIR filter implemented in programmable logic can operate at data rates above 100 million samples per second, versus 3 MSPS for a typical DSP.

Design evaluation

The traditional methodology for designing a functional block within a system consists of two phases: system specification and hardware implementation. Both phases require multiple iterations and can involve a four-to-six-week process just to ensure that a single functional block operates to specification within the system. Creating this filter from the ground up, using either VHDL or other design entry methods, would have required too much development time. So we decided to use the Altera FIR compiler and Opencore evaluation system, which reduced our risk and sped the design process by allowing us to evaluate and complete the filter design prior to purchasing the core (see Figure 3).

Figure 3 - Design cycle comparison

The FIR compiler can greatly reduce both the development time and the complexity of a filter design.

In order to help parameterize and integrate the IP cores megafunctions into designs we used DSP Megawizard (a GUI-based tool) plug-ins. The plug-ins work together with Matlab and Simulink software from The Mathworks (Natick, Mass.) to provide a system-level design and implementation system.

The FIR Megawizard facilitates system-level design by automatically generating an optimized implementation of the specified filter. The tool supports two alternative design flows, one that begins in the tool itself, another that commences in Matlab. In both cases, the tool generates Matlab models for system-level verification and VHDL and Verilog models for RTL simulation.

The Opencore evaluation feature allowed us to test-drive the FIR compiler that generates parameterized FIR filters, customized for behavior and performance. Using our existing system-level design and verification tools, we fully exercised and evaluated the system including instantiation into the system, compilation, simulation, and verification prior to purchasing the IP. This evaluation provided us with first-hand functional, timing, area, and other technical data that allowed us to make an informed decision on whether to license it.

The FIR generation

The FIR compiler allowed us to customize the filter parameters to meet the needs of this application. This tool generated a customized instance of the megafunction that was instantiated directly into the TIMS design.

We launched the plug-in manager to begin the FIR filter generation process. Using the graphical user interface, we specified that we wanted to create a new custom megafunction. We then selected the FIR compiler function from the DSP drop-down list and assigned a filename.

The FIR compiler automatically generated a set of coefficients based on our specified frequency response and sample rate. To generate a better filter, one normally "windows" the coefficients with a mathematical function. Each type of window exhibits unique characteristics. Generating one requires a simple click of a radio button. In addition to the window type, we also specified the number of taps, the precision of the input data, and other parameters. We were able to easily adjust the number of taps and other parameters until we were satisfied with the results When we had specified all the design parameters, we then clicked the "apply" button and the tool automatically plotted the frequency response and coefficient values.

Among other things, the FIR compiler can generate fixed- or floating-point coefficients or can import them from system-level design tools such as Matlab via a text file. In this case, we imported the coefficients directly from a DSP design tool. The tool can scale the coefficients or use them as is. The coefficients are displayed in the Scaled And Rounded Coefficients box. The wizard detects any symmetry automatically, and selects an optimal filter architecture.

In the next step, we specified whether to use full or limited precision for the filter output. The FIR compiler automatically determines the output bit width based on the actual coefficient values and the input bit width. These two parameters define the maximum positive and negative output values. The wizard extrapolates the number of bits required to represent that range of values. For full precision, we would have had to use the number of bits in the system. Since we chose limited precision, the wizard gave us the option of truncating or saturating the most-significant bit (MSB) and/or rounding or truncating the least-significant bit (LSB). We then selected the architecture of the filter (for example, parallel or serial, pipelined or not, and the number of input channels). A number of tradeoffs exist for different architectural options (see the table). The Resource Usage box displays the estimated size in EABs or logic cells and the number of clock cycles required to complete the FIR computation.

It's interesting to note that increasing the number of taps results in a larger design. Within the wizard, it's possible to reduce the number of specified taps and then check the resulting filter response to see if it still meets the system requirements. Thus, the tool provides a quick, iterative process to optimize filter performance. Using both the wizard and the evaluation feature, we were able to design the required filter with a minimal number of device resources. The FIR compiler wizard generated VHDL and Verilog for register-transfer-level simulation using tools from a number of EDA vendors.

After simulating the system and finding the results agreeable, we were ready to implement the entire system. Compilation was a straightforward and push-button operation. Once the compilation was complete, we simulated the entire design to verify device timing. After licensing the megafunction, we were able to program a PLD and verify proper operation in hardware. The hardware implementation of the filter worked as simulated, and the process opened up numerous possibilities for filters and IP cores in the future.