Ideally, most circuits designed for the scanning process have a single clock, which generally allows the easiest flow of logic within the circuit and resolves most timing issues. However, multiple clock domains change this dynamic, as more stops exist along the way to the final destination. Using scan chains simplifies the process of test pattern generation. A scan chain connects the flip-flops in a design to form a shift register. The function of a scan chain is to attach the flip-flops in a circuit to a shift register. Each flip-flop in a scan chain thus contains two sources of input: the output of a combinational circuit for functional operation and the output of the previous flip-flop in the scan chain. That's all well and good, except that one big problem clock skew can tangle the entire chain, undermining the integrity of the signals and adding uncertainty to the testing process. But don't start sweating just yet by adhering to a few basic rules, designers can virtually eliminate the dangers posed by clock skew in multiple-domain systems.

Figure 1 - A Simple Synchronous Circuit

F1 is the source flip-flop and F2 is the destination flip-flop. Given sufficient skew, the clock on F2 triggers much later than the clock on F1, thus capturing the value expected in the next cycle and hindering the operation of the circuit.

A skewed perception

Clearly, a single clock domain alleviates much of the worrying in the test process. This restriction helps to guarantee the correct shifting of data through the scan chain and the proper capturing of combinational logic outputs. Most complex designs, however, are likely to have numerous clock domains, thus increasing the chance of unwanted clock skew.

Clock skew (Tsk) the variation in timing between clocks on flip-flops within a clock domain stems from a large fanout of clocks in the circuit. Clock skew often limits the speed at which a circuit can operate, and even worse, can invalidate the operation of the circuit. Though designers can tightly control the skew between clocks within a single domain to fall below a desired limit, it's often difficult if not impossible to control and therefore hold skew between different clock domains.

A synchronous design with a single clock domain can be abstracted (see Figure 1). The proper operation of the circuit depends on the three timing parameters associated with a positive-edge-triggered flip-flop. Setup time (Ts) is the time interval immediately preceding the positive transition of the clock input, during which the system must maintain the data at the input to ensure its recognition. Hold time (Th) is the time interval immediately following the positive transition of the clock input, during which the system must maintain the data at the input to ensure its continued recognition. The combinational-logic delay (Tcomb) is defined as the time required for signals to traverse the combinational logic. Propagation delay (Tp) is the time taken for changes in the clock input to affect the outputs. Proper operation thus requires Tsk < [Ts(F2) + Tcomb + Tp(F1)].

For a scan chain (ignoring all wire delays), Tcomb is 0, because a scan chain contains no combinational logic between the flip-flops. Thus Tsk < [Ts(F2) + Tp(F1)].

Designers often use special routing techniques for clocks to guarantee that this equation holds. Failing to meet this requirement sabotages the scan operation and probably the fast functional paths in the design as well. Therefore, good design practices are essential.

Since multiple clocks operate independently, it's impractical to control the skew between the different clock domains. The multiple clock domain problem in scan splits into two different types: shift problems, which occur when the scan chain is shifting, and capture problems, which occur during the capture cycle. Solutions to the shift problem focus on the need to guarantee correct operation so that the patterns generated by the automatic test pattern generation (ATPG) tool apply to the inputs of the combinational logic. The capture problem, in contrast, concerns the need to know the order of the clocks, information used in generating the vectors for ATPG.

Shifty clocks

The shift operation of scan applies the generated patterns to the inputs of the combinational logic and enables the observation of the corresponding outputs. During the shift operation, the scan chain operates as a shift register. Given the constraints described previously, a shift register built using flip-flops will operate correctly in a single-clock system, that is. However, employing a shift register with more than one clock can create problems (see Figure 2). Here, flip-flops F1 and F3 are clocked with a signal CK1, while flip-flop F2 is clocked with CK2. If the two clocks are misaligned, they may become offset by some delay. Even if both were primary inputs, limitation in tester resolution would make it difficult to align them perfectly on the tester. Suppose CK1 triggers before CK2. In this case, CK1 loads a value into F1, and then in the same cycle, when CK2 triggers, F2 loads with the same value as in F1. On the next cycle, flip-flop F3 will load that value one cycle too early.

Figure 2 - The Original Design

Clock skew turns this circuit into a timing glitch waiting to happen. Depending on which clock triggers first, the output changes.

CK1 triggering earlier than CK2 thus leads to two unwanted consequences. F2 can't hold an independent value and so no longer operates as a storage element. After that happens, flip-flops after F2 will receive their values one cycle too early, fortunately. Now suppose that CK2 triggers before CK1. In this case, since CK2 comes first, F2 loads the output of F1 from the previous cycle (which is the correct operation), and then F1 loads the new value. So far so good. Unfortunately, this operation merely delays the inevitable timing flaw flip-flop F3 suffers the same problem that F1 and F2 did earlier. Since CK2 triggers first, F2 changes values before flip-flop F3 has a chance to load the value from the previous cycle.

Multiple clocks can cause some of the flip-flops to behave as buffers, eliminating their storage capability. This shift in identity clearly invalidates the ATPG patterns that are applied to the circuit, as the system applies unexpected inputs to the combinational logic.

Timing is everything

Numerous clock domains aren't always easy to coordinate in the circuit, but fortunately, several remedies are available. Level-sensitive scan designs (LSSDs) or two-port flip-flops enable the use of a separate clock for test. This option does come with two costs, however. First, such scan cells are typically much larger than the MUX-D flip-flops that we typically use. Second, they require the routing of additional clocks, which must submit to accurate timing. Another option is to keep flip-flops of different clocks in different scan chains, the safest and easiest way to eliminate skew problems. Unfortunately, a design can usually include only a limited number of scan chains. The limit depends on how the designers use the tester. If they employ a special scan board on the tester, then the limit is usually 4 or 8. If they use the normal pins of the tester, then the limit equals the number of pins that can be multiplexed with scan-in and scan-out. Now, if having separate scan chains for each clock domain exceeds the limit, then we have to resort to the next solution.

Figure 3 - Design Under Repair

Adding a buffer or lockup latch while adhering to the late-first rules helps to nullify the effects of clock skew.

It's also possible to combine flip-flops of different clock domains in the same chain (see Figure 3) by following a relatively simple process. Form subchains for each clock domain and place them in the order prescribed by late-first rules 1 and 2 (see below). If necessary, add buffers or lockup latches between the subchains. The buffer delay should be large enough to overcome any skew between clock domains. Latches adding half a cycle also work.

One way to reduce the domain-skew problem is to control the clocks from the primary inputs. If the designers can control the clocks well enough, the buffers added in the final step may be unnecessary. However, it's usually best to use them. The clocks should be applied according to late-first rule 1.

Late-First Rule 1: Clock flip-flops near the end of the chain (closer to scan-out) first.

Following the late-first rule guarantees that the scan chain will shift properly. In some cases we lack a great deal of control over the clocks of the separate clock domains, perhaps because they are derived from the same clock. In that case we need to make sure that flip-flops with ýlate clocksý should come early in the scan chain, as late-first rule 2 summarizes.

Late-First Rule 2: Place flip-flops with the latest clocks at the front (closer to scan-in) of the scan chain.

Flipped flops

Some designs mix positive- and negative-edge- triggered flip-flops from the same clock. It's best to think of and handle these flip-flops as located in two different clock domains. As above, designers can place different clock domains in separate chains, or combine subchains. Negative-edge-triggered flip-flops placed in a separate chain pose no problem. If we are combining the two domains, however, we can't control the clocks of the two domains, since they are derived from the same clock. So we treat the negative clock as a late clock and, adhering to rule 2, placed the negative-edge-triggered flip-flops first in the scan chain (see Figure 4).

Figure 4 - The Negative Edge

Rule 2 makes the negative-edge-triggered flip-flop easy enough to handle: simply treat it as a late clock, placing it first in the scan chain.

If a design contains gated clocks, the scan rules mandate the addition of multiplexors to bypass these clocks with one of the system clocks or a scan clock. Unfortunately, during synthesis, multiplexors of different styles may create large skew between the gated clocks. The simplest solution is to place all such flip-flops in a single chain and add buffers between all the flip-flops of that chain.

A less area-intensive approach determines which clocks come out of which subdomain, groups subdomain flip-flops together, and adds buffers only between subdomains. This alternative can minimize the number of buffers required, but does require more analysis.

So many clocks, so little timing Shift operation, unfortunately, isn't the only generator of clocking problems. Similar timing problems can occur during capture. In certain situations, where little or no combinational logic lies in the normal path between a pair of flip-flops of two different clock domains, capturing the correct signals in the flip-flops is a tricky business. Predicting the expected value is the most significant function in capture operation (see Figure 5).

Suppose X1 = 1, a = 0. Then, if CK2 triggers before CK1, F2 captures the value on its data input (which is a 1) before F1 does, and the final value of b will be 1. If, however, CK1 triggers before CK2, F1 captures the value on its data input first, changing a to 1. Then the data input on F2 will be 0 when CK2 triggers. If an ATPG tool assumes that all clocks trigger at the same time, then it will yield results similar to the former case. However, if in silicon, CK2 triggers after CK1, we capture an expected value.

The problem within the example arises because we can't predict the skew variation between the different clocks. Limited tester granularity is also a concern, as it isn't possible to align separate clocks to allow for true simultaneous triggering of all the clocks. Forcing CK2 to trigger on the tester before CK1 would, of course, solve problems for F2 but create similar problems for F3.

The solution is to provide the ATPG tool with information about the clocking sequence, and have it generate patterns based on this clocking sequence, rather than assuming that all clocks trigger at the same time. Then when the tester works on the patterns, it uses the same clock sequence. In our example, the two clocks CK1 and CK2 are sequenced. Since CK1 rises first, F1 and F3 capture the outputs of the OR gate and the AND gate respectively, as with normal ATPG. F2, however, captures the outputs of the inverter, but only after F1 has changed its contents.

Figure 5 - The Clock Phased Circuit

Clock phasing adds a ývirtual bypassý to the netlist (the red line), allowing the test engineer to view the circuit as itýs supposed to function, regardless of clock skew.

Internally the ATPG tool transforms the netlist (the actual circuit doesn't change) by adding a virtual bypass (the colored line in Figure 5). In this model, we see that F1 is no longer providing a real input pattern to the combinational logic, but still allows the test engineer to observe the output of the OR gate. The combinational cone driving F2 has grown to include the OR gate and the inverter. We have used this technique quite effectively on many designs, achieving high fault coverage with no mismatches in timing simulation, or on the tester.

Scan sees wide use today because it facilitates ATPG, resulting in high-quality chips. The presence of multiple clocks can set up a significant roadblock to correct scan operation, so understanding how to handle multiple clocks properly can mean the difference between accurate testing and production nightmares.