Tools and Technologies Products and services for IC and electronic system design

Tools and Technologies

Functional verification Suresolve is automatic functional verification software developed to merge design and verification tasks for ICs and intellectual property. It's tightly integrated with Surecov, coverage analysis software already available, allowing verification to start as soon as designers are coding at the RT level--automating recurring cycles in the design flow without changing the existing environment. Suresolve generates RTL test benches for verification on small blocks as well as integrated system design. The tool analyzes the flow of control and data through a Verilog RTL design, automatically building a set of functional tests to exercise 90 to 100 percent of all reachable constructs. It highlights unreachable constructs for further investigation by the designer, who can use the tool to build the first test suite for a new design, then automatically update the test suite and test bench each time the design changes. Suresolve also allows the user to specify individual code statements and complete functional paths or test sequences and, after coverage analysis, to build incremental tests to increase coverage. Its results display uses highlighted source code and bubble diagrams to show all FSMs, code blocks, and arcs found within the design description. Available now, Suresolve and Surecov support Verilog and run under SunOS, Solaris, HP-UX, and Windows NT. Sold separately, Suresolve costs $55,000; bundled with Surecov, it starts at $65,000. Surefire Verification, Inc., Campbell, Calif. Contact (408) 374-4100 or www.surefirev.com.

Waveform generator and simulator Waveformer Pro v5.0 incorporates an interactive, instant feedback and continuous simulation engine that adds support for FPGAs and the Timing Diagram Markup Language (TDML) and also writes simulation code. The tool's other new features include spreadsheet-based entry of test vectors, VCD file import, modeless dialogs, automatic labeling of counter and shifter signals, stimulus export to the Xilinx Foundation Kit simulator, a report/editor window for displaying design status information, extended undo and redo, time markers that compress time, and stimulus generation for HP pattern generators. For Windows 95, 98, and NT, Waveformer Pro v5.0 is priced at $1,750; for Solaris, SunOS, and HP-UX, it starts at $2,000. SynaptiCAD, Inc., Blacksburg, Va. Contact (800) 804-7073 or www.syncad.com.

Debugger The Virsim debugging environment now includes high-performance data compression and support for the Linux operating system. Virsim handles large designs using a proprietary VCD+ file that's optimized for analysis. The new compression feature reduces file size for simulation data by 700 to 1,000 percent while maintaining a very low simulation drag. The new compact database is compatible across all platforms, allowing results from simulations on Unix servers to be analyzed on a PC or vice versa. Virsim-VS1 floating licenses, available now, cost $4,900 each. The debugger runs under Linux, Solaris, SunOS, HP-UX, Irix, and AIX, as well as Windows 95 and NT. Summit Design, Inc., Beaverton, Ore. Contact (503) 643-9281 or www.summit-design.com.

Crosstalk analyzer Crosstalk, an interactive prelayout crosstalk analysis tool, is an option for the Linesim signal integrity simulator. As a simulation environment for analyzing and predicting crosstalk effects on high-speed PCBs, it enables design engineers to define interconnect scenarios likely to be affected by crosstalk--from simple pairs of side-by-side nets to detailed bus topologies on complex backplane designs. The tool focuses on preroute analysis, allowing users to define "crosstalk neighborhoods" that specify the geometric relationships between adjacent conductors. Using an integrated field solver, the software automatically converts geometric data into coupled electrical data and shows the resulting crosstalk simulation waveforms in an oscilloscope display. Available immediately, the Crosstalk option is $3,000. Linesim, which runs under Windows 95, 98, and NT, costs $3,995. An EMC analysis option is available for $1,000. Hyperlynx, Inc., Redmond, Wash. Contact (425) 869-2320 or www.hyperlynx.com.

SDRAM controller core Stargate's SDRAM controller megafunction meets the emerging 66-MHz design requirements when used with Altera's Flex 10KE devices. It supports newer processors, such as the PowerPC, that require an SDRAM interface instead of a DRAM interface, and includes a simple request/handshake interface on the application side and a configurable interface on the SDRAM side. Three 32-bit programmable configuration registers provide designers with a variety of configuration alternatives, enabling the core to interface with 4-, 16-, 64-, or 128-Mbit SDRAM modules in 34, 38, or 316 configurations, each with a CAS latency multiple of either 2 or 3. The megafunction is currently available for evaluation at no charge; source code and simulation files are also available. An encrypted netlist begins at $5,000 and includes a development test bench. Stargate Solutions, Inc., San Jose, Calif. Contact www.sgates.com.

200,000-gate PLD A member of the Flex 10K family, the 200,000-gate EPF10K-200E programmable logic device includes dual-port RAM in flexible configurations up to 16 bits wide, 9,984 logic elements, and 24 Embedded Array Blocks (each with 4 kbits of RAM). The 2.5-V chip also features fast operation and pin-for-pin compatibility with 3.3-V Flex 10K family members. It's fabricated with an optimized 0.25-µm, five-layer-metal SRAM process and offers 140-MHz 16-tap, 8-bit FIR filter performance. The EPF10K200E also uses Altera continuous Fasttrack Interconnect feature, designed to fully leverage process metal layers, resulting in additional performance gains and minimum die area. The device is available now in 600-pin BGA and 599-pin PGA packages, starting at $215 in high-volume quantities. Altera Corp., San Jose. Contact (800) 9-ALTERA or www.altera.com.

Hardware functional verification Xcite-1000 is a design verification tool that couples reconfigurable computing (RCC) hardware with verification and debugging software to attack functional verification throughput. It offers new technology that combines software simulation and an RCC hardware engine that uses an array of high-density programmable logic ICs. The tool is a complete logic verification system operating at 10,000 to 100,000 cycles per second with full simulation interaction. Whether the design is described at the Verilog HDL behavioral, RT, or gate level, the RCC compiler transparently maps the design onto RCC computing elements and provides a tight integration to the Xcite-1000 software simulator for interactive debugging. The Xcite-1000 RCC hardware fits easily inside a Sun Ultra 30 or Ultra 60 workstation and connects directly to its PCI backplane. The Altera components and the number of PCI boards selected determine its capacity. Each board handles designs of up to 250,000 gates using Altera's 10K250 programmable logic device and contains 2 Mbits of SRAM that's upgradable to 8 Mbits to simulate memory models. The tool, available now, comes with a million-gate capacity, the software simulator, and the RCC compiler and costs $295,000; an upgrade to 2 million gates is another $95,000. Additional software licenses for design teams are $45,000 each. Axis Systems, Inc., Sunnyvale, Calif. Contact (408) 588-2000 or www.axiscorp.com.

Fault coverage TurboFCE, a fault coverage enhancer for Verilog RTL designs, instruments RTL code by adding zero-delay buffers so that a user can perform fault grading. It takes advantage of the correlation between a variable in the RTL design and wires in the synthesized gate-level circuit of that design so that users can inject faults at the inputs of the buffers. As a result, RTL fault grading produces fault coverage close to a gate-level fault grader. The gate-level fault grader, Turbofault, has improved speed and comes with a comprehensive Tcl/Tk GUI that operates on Sun UltraSparc workstations. Starting at $10,000, TurboFCE is available now for Unix workstations, including Sun and Sun UltraSparc, and Windows NT. In addition, Turbofault and Turbocheck are also now available for Windows NT; customers with maintenance agreements receive upgrades free. Syntest Technologies, Inc., Sunnyvale, Calif. Contact (408) 720-9956 or www.syntest.com.

Fast 3.3-V CPLD family A family of high-density programmable logic devices combines high performance and 3.3-V operation. The IspLSI 2000VE devices are based on the architecture of the Superfast IspLSI 2000E CPLDs. The 32-macrocell IspLSI 2032VE features 4-ns/200-MHz (t _pd /f _max ) performance, and the 128-macrocell IspLSI 2128VE runs at 5 ns/180 MHz. IspLSI 2000VE devices feature input-to-clock setup times to 2.5 ns and clock-to-output delays to 3.0 ns. To support designs migrating to 3.3-V operation from 5 V, all devices provide 5-V-tolerant I/O pins. They feature programmable pull-up resistors, hot-socketing capability, and programmable open-drain outputs. Available now, the 200-MHz IspLSI 2032VE costs $11 per thousand and comes in 44-lead TQFPs and PLCCs as well as the 49.0-mm ² 49-ball BGA package. The 180-MHz 2128VE, which costs $22.70 per thousand, comes in a variety of packages. including 100- and 208-ball BGAs and compact TQFPs . Lattice Semiconductor Corp., Hillsboro, Ore. Contact (503) 681-0118 or www.latticesemi.com.

FPGA development suite FPGA Integrated Development System Version 6.0 improves placement and routing while adding OrCAD CAE system support, an FPGA power calculator, and logic and RAM compilers. The tool runs on PC, Sun, and HP workstations and supports incremental design change capabilities, improved VHDL and Verilog synthesis, and support for conversions from other FPGA technologies. It allows customers to target either an Atmel or a competitor's FPGA. It's available free of charge for a limited period from Atmel's Web site. Atmel Corp., San Jose, Calif. Contact (408) 441-0311 or www.atmel.com.

Design capture and simulation tool Version 6 of T-Spice Pro, an IC design capture, simulation, and data-viewing system, includes new optimization options, remote simulation over a network, parameter sweeping, more flexible behavioral modeling, and advanced postprocessing support. T-Spice includes the latest MOSFET model parameters (including BSIM3 v3) and full support for advanced parasitic models and automatic size-based model selection. Designers can link proprietary device models through a built-in C interpreter or by compiling the model into a dynamically linked library before simulation. T-Spice Pro V6 for Windows 95, 98, and NT is available now and starts at $4,495, and a Unix version will be available this quarter. Tanner EDA, Pasadena, Calif. Contact (626) 792-3000 or www.tanner.com/eda.

System and board tools Synario System Designer and Board Designer add system and board design capabilities to Synario Programmable IC Designer. The latter's Project Navigator now supports a level of hierarchy as it would a complete project, as well as multiple design domains (digital, analog, PCB) in a distributed environment. The intelligence provided by the on-line connectivity database ensures the integrity of the entire linked project structure by alerting parent projects of changes in child projects, such as interface alteration and library usage.

Synario System Designer targets electronic systems that require the coordination of multiple designers, product development teams, or both. It provides an environment to decompose a complex design into manageable parts and then make those parts available to domain-specific teams. System Designer supports VHDL simulation for behavior and timing simulation using Model Technology's Vsystem or Modelsim and VHDL, Verilog, and Spice netlisting. Synario Board Designer, a subset of System Designer, addresses board design and supports board simulation using VHDL with Model Technology's Vsystem and Modelsim.

System Designer and Board Designer are shipping now for Windows 95 and NT. They start at $3,995 and $2,495, respectively. Introductory pricing for both products is available for new and current Synario customers. Minc, Inc., Redmond, Wash. Contact (888) 796-2746 or www.synario.com.

RDRAM verification The Direct Rambus DRAM Verification Kit includes simulation models, performance modeling, and debugger software to improve the verification process for Rambus DRAM­based memory controllers and systems. The Direct RDRAM verification kit includes simulation models for Direct RDRAM and Direct Rambus ASIC Cell (Direct RAC), performance modeling based on the recently announced Autotest and a customized Direct RDRAM debugger. Direct RDRAM models are now incorporated as one of Memorymodeler's supported classes, which include DRAM, SRAM, SDRAM, SGRAM, DDR, SSRAM, ESDRAM, flash, PROM, SEPROM, and FIFO cores. The Direct RAC is a library macrocell used in ASIC designs to interface the core logic of an ASIC to the Direct Rambus Channel. Pricing starts at $15,000. The kit includes support for both VHDL and Verilog and runs under Microsoft Windows 95 and NT, SunOS, Solaris, and HP-UX. Denali Software, Inc., Palo Alto, Calif. Contact (650) 325-7241 or www.denalisoft.com.

Emulation software Virtualogic 2.1 enhances the speed and ease of use of Ikos's FPGA-based emulation. Users now possess 100 percent visibility into their designs and three- to five-fold design compilation speed improvements, and they can offload FPGA compiling steps onto PCs and Unix workstations. Virtualogic 2.1 is being shipped now to all customers under maintenance at no additional cost. Ikos Systems, Inc., Cupertino, Calif. Contact (800) 223-3987 or www.ikos.com.

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integrated system design  February 1999