Tools and Technologies Products and services for IC and electronic system design

Layout design suite Ladee is an integrated, full-custom layout design and conversion tool suite that creates full-custom layouts with design reuse in mind for different foundries and applications. It addresses signal integrity problems like crosstalk and optimizes layouts for performance and power. The suite includes modules for layout entry (Lace Edit), extraction, verification, compaction, and hierarchical conversion (Lace). Ladee gives the user active control over the interconnect capacitance created during the physical design process. It recognizes and resolves sophisticated deep-submicron design rules and solves timing and signal integrity problems automatically. It runs on Sun and HP workstations and PCs under Unix and Linux. Pricing begins at $69,000. Rubicad Corp., San Jose, Calif. Contact (408) 995-3334 or www.rubicad.com.

Parasitic extraction Fire & Ice 2.0 accelerates parasitic extraction run times more than 300 percent over previous versions of the tool without loss of accuracy. Designers of multimillion-transistor, multilayer metal chips can now extract their entire designs in hours with bounded accuracy and immediately begin timing analysis with such third-party tools as Cadence's Pearl or Synopsys's Pathmill. Version 2 improves its 3D Adaptive Analytical Extraction technology and optimizes both its algorithms and methodology, minimizing the amount of data produced during extraction. It runs on Sun and HP workstations. Pricing starts at $150,000. Simplex Solutions, Inc., Sunnyvale, Calif. Contact (408) 617-6100 or www.simplex.com.

Logic simulation Gate-cruncher performance optimizations added to the Affirma NC Verilog logic simulator include a set of compaction algorithms that increase the simulator run-time performance threefold for gate-level circuits with full timing capability. The simulator automatically invokes the gate-cruncher algorithms for the gate-level portions of the design, enhancing performance with full timing capability, including circuits that use SDF files for timing. The Affirma NC Verilog simulator runs under Unix on Sun and HP workstations and costs $40,000 for a floating license or $32,000 for a node-locked license. Cadence Design Systems, Inc., San Jose, Calif. Contact (800) PHON-CAD or www.cadence.com.

PowerPC emulator The Powertap JTAG/COP emulator for Motorola's MPC8240 PowerPC communications microprocessor offers full visibility and control of the processor's core registers and memory as well as its instruction and data caches. Paired with the Codetest software analyzers, the tool provides developers with real-time source-level tracing and performance, memory, and code coverage analysis. It offers a cache display window, MMU support, and fast flash programming. The debugger includes a comprehensive CPU browser covering the MPC106 PCI bridge-chip register set, providing bit-level detail of the registers. It's available for PC and Sun host systems starting at $7,995. Applied Microsystems Corp., Redmond, Wash. Contact (800) 426-3925 or www.amc.com.

To voice an opinion on this or any Integrated System Design article, please email your message to miker@isdmag.com.

integrated system design  March 1999