Tools and Technologies Products and services for IC and electronic system design

C-to-HDL compilers RTLC2Verilog and RTLC2VHDL support the compilation of C to synthesis-ready VHDL and Verilog. To provide support for RTL-C synthesis coding styles, the tools explicitly divide the algorithms that handle combinational and sequential logic constructs from the higher-level constructs used for behavioral design. RTLC2Verilog, available now, runs under Unix and Windows. RTLC2VHDL will be available in July for Unix and Windows systems. Prices for both products begin at $75,000. C Level Design, San Jose, Calif. Contact (408) 369-0555 or www.cleveldesign.com.

Power analysis The latest release of Pspice Power Analyzer ports the Simplis simulation engine to Windows 95, 98, and NT and integrates it with OrCAD's Pspice. The Simplis simulation engine extends OrCAD's switch-mode power supply (SMPS) simulation offering beyond Pspice. The tool provides extended library offerings, supporting a subset of the existing Pspice library with additional devices provided by the company. The Pspice Power Analyzer is sold as an add-on package to an existing Pspice installation and is available now for $5,995. Power Design Tools, Inc., Los Altos, Calif. Contact (650) 917-5700 or www.pdt.com.

RTL power estimation tool Powersure enables IC and SOC designers to estimate power consumption in behavioral and RTL source code. The tool uses real circuit activity to analyze power information, in contrast to other tools that can only estimate power based on a probabilistic propagation of circuit activity. Targeted for power-sensitive designs, such as the chips inside mobile phones and handheld portable electronic devices, the tool estimates the four factors that affect power dissipation: capacitance, clock frequency, supply voltage, and switching activity. It lets designers look at individual or multiple simulation runs and sort them according to power consumption. They may also select a test case to see the design hierarchy detail and browse to "hot spots" or those signals in the RTL source that consume too much power. Powersure is available now, starting at $50,000. TransEDA, Ltd., Los Gatos, Calif. Contact (408) 395-5347 or www.transeda.com.

Merced cosimulation A design environment for the Intel Merced processor includes the XTK and AC/Grade tools and can perform a complete cosimulation, giving users the ability to perform Signal Integrity Analysis (SIA) and Simultaneous Switching Output (SSO) noise analysis. The tools can simulate the interconnect timing, signal I/O, power/ground net, and package effects simultaneously. They can also analyze the processor's driver and receiver buffers as well as the effects of power and ground bounce. The design environment is available immediately starting at $37,500. Viewlogic Systems, Inc., Marlboro, Mass. Contact (800) 873-8439 or www.viewlogic.com.

HDL simulator Modelsim Elite Simulator Version 5.3 adds a performance analyzer, code coverage capability, and a Verilog RTL performance improvement of up to five times the speed of previous Modelsim versions. The performance analyzer identifies HDL simulation bottlenecks, working with VHDL and Verilog at all levels of abstraction. Performance results appear in a hierarchical display, allowing designers to identify slow spots in their simulations. The code coverage feature enhances overall efficiency of the verification environment by measuring the percentage of an HDL model exercised by a test bench during simulation. The tool includes a language-neutral license facilitating simulation of either VHDL or Verilog designs with one simulator and one license. Modelsim Elite 5.3, available this quarter, costs $20,000. Existing customers will be notified of upgrade pricing. Model Technology, Inc., Portland, Ore. Contact (503) 641-1340 or www.model.com.

RTL design tool Nova-ExploreRTL is interactive design authoring software that locates and corrects problems and characterizes critical design metrics while creating designs in RTL code. It ensures that designs are consistent with language standards and tool requirements, are reusable and portable, and are predictable with regard to timing and testability. It identifies untestable logic, asynchronous loops, and snake paths in the RTL code. It also analyzes designs of third-party IP against built-in design reuse guidelines, a design team's specific reuse guidelines, and those suggested in the Reuse Methodology Manual. Nova-ExploreRTL for Verilog is currently available for the SunOS, Solaris, and HP-UX operating systems. The VHDL version will be available this quarter. Single-unit pricing starts at $35,000. Avanti Corp., Fremont, Calif. Contact (510) 413-8000 or www.avanticorp.com.

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integrated system design  May 1999