Tools and Technologies Products and services for IC and electronic system design

System tool suite Comet 2.0 is an interactive system-level engineering tool set that enables engineering teams to specify, architect, and design fully executable virtual prototypes that model, verify, and debug complete hardware/software systems in ASIC, PCB, and SOC designs. The tool set helps system architects quantitatively experiment early in the engineering process with partitionings of hardware and software, the choice of processor and its configuration, and operating system options. It allows designers to execute application software on retargetable Virtual Processor Models (VPMs) at speeds in excess of 150 MIPS while preserving timing accuracy across the hardware/software interface. It supports more than a dozen VPMs, covering such microprocessors as the ARM7 and ARM9 families with Thumb extensions, Hitachi SH3, Intel 80386, Motorola 68000/68030, MIPS R3000 and R4000 families, Sparc V8, and NEC 41xx. It works with industry-standard Verilog and VHDL hardware simulators including Model Technology, Cadence, Synopsys, and Fintronic; supports C and C++ for software; and runs on both Solaris and Windows NT. Comet 2.0 is available now, priced at $50,000 for a floating license. Each VPM costs $10,000. Vast Systems Technology Corp., Santa Clara, Calif. Contact (408) 566-1940 or www.vastsystems.com.

Back-end tool suite First Encounter is an integrated set of tools centered on the Fasttrack database architecture, which requires less than 30 percent of the memory of existing tools. It combines optimized chip-level partitioning, unified floorplanning and placement, trial routing, parasitic extraction, timing delay calculation, timing analysis, and timing optimization into a single environment. Starting with a Verilog netlist and timing files from synthesis, the system produces an optimized and timing-correct final placement file for detailed routing by the customer's or ASIC vendor's existing router. Users can take a million-gate design through an entire flow in less than four hours, reducing design cycle time for each iteration. The tool utilizes the Amoeba hierarchical locality-based placement algorithm, which combines the advantages of both flat and hierarchical design styles. Amoeba retains the logic hierarchy in the physical domain, presenting it in an understandable way to the logic designer very early in the design cycle. The "floorplan" is a simplified view of the underlying cell placement file, and the tools to manipulate the floorplan simply act as user input to the placer. First Encounter is available now on Unix platforms. The base package (a single-job floating license) costs $180,000, including optimized chip-level partitioning, unified floorplanning and Amoeba placement, trial routing, parasitic extraction, timing delay calculation, and timing analysis. Silicon Perspective Corp., Santa Clara, Calif. Contact (408) 327-0900 or www.siperspective.com.

Physical design tool Dolphin is a physical design system for multimillion-gate SOC designs of 0.25 µm and below. Using global design technology, it complements front-end design tools by using currently produced standard netlists and floorplans. The system features built-in design convergence, which provides predictable design closure. Rather than shuttling back and forth among separate, sequential algorithms and tools, the algorithms achieve a global solution by simultaneously analyzing all dimensions of physical design, including logic optimization, placement, routing, timing, clocking, power routing, crosstalk, and other effects. A new capability called fluid-block design starts with floorplan data provided from the host design environment and analyzes circuit elements within logic blocks, shifting their physical placement and associated wires if the placement change results in overall design improvement. The system, which plugs seamlessly into existing industry design flows, accepts netlists and floorplans from Synopsys and Cadence tools and produces GDS-II output. Dolphin runs on commercially available uniprocessor- and SMMP-based Unix or Windows NT platforms. Pricing starts at $419,000. Monterey Design Systems, Inc., Sunnyvale, Calif. Contact (408) 747-7370 or www.montereydesign.com.

Modeling and analysis tool Layin 2.0 is a substrate modeling and noise analysis solution targeted at RF, analog, and mixed-signal IC designs. It enables designers to model and analyze substrate noise coupling effects in integrated circuits before fabrication, meaning significant cost savings through fewer design iterations, reduced die sizes, and the integration of more functionality on smaller chips. The tool takes its information from process doping profiles and builds a three-dimensional model of the substrate that is more accurate and more adaptable to new process technologies. It also concentrates on modeling local effects, as opposed to other tools that model substrate effects across a full chip. The proprietary technology characterization allows a designer to model any structure with a minimum of 80 percent accuracy. Layin 2.0 is available immediately for Hewlett-Packard and Sun Unix workstations. Pricing starts at $100,000. Snaketech Corp., San Jose, Calif. Contact (408) 557-6838 or www.snaketech.com.

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integrated system design  June 1999