Tools and Technology

Products and services for IC and electronic system design

Verification tool Solidify is a static RTL analysis tool that verifies the functional behavior of a block coded in Verilog HDL or VHDL, without using vectors. The tool verifies that the intended behavior found in the user's functional specifications is correctly coded into an HDL. Solidify's static approach avoids any simulation bottlenecks, which improves verification times. All the behaviors of a block can be verified, including difficult corner cases. Solidify is supported on workstations running the Sun Solaris, and Microsoft Windows NT operating systems. Pricing for Solidify begins at $30,000. HDAC, Inc., Alameda, Calif. Contact (510) 864-1657 or www.hdac.com.

Measurement tool VCOBIST (voltage-controlled oscillator BIST) enables accurate, high-speed jitter measurements in silicon with complete test times as low as 20 milliseconds (ms). The VCOBIST approach promotes test reuse by giving designers a way to wrap test functions around specific design intellectual property (IP). There are no analog circuits in the VCOBIST Test IP. Insertion into the design process is done using synthesizable Verilog or VHDL code. Control of the VCOBIST Test IP is performed through an 1149.1 interface. In addition to measuring jitter, VCOBIST measures the common specifications for PLLs or VCOs. For a 75-MHz PLL in a CMOS process, VCOBIST measures peak-to-peak jitter with better than 50-ps accuracy (typical) and performs the full measurement in less than 40 ms. A high-speed bipolar process implementation achieves better than 8-ps accuracy with a full measurement time of less than 20 ms. Maximum performance can be achieved for an on-chip gate count of less than 2,000. The entire implementation of VCOBIST is done on-chip or it can be implemented in a chip set, which is then mounted in the ATE system or on the load board. VCOBIST is available for $45,000. Pricing is per project and includes Verilog/VHDL libraries, documentation, and the VCOBIST Test IP interface description. Fluence Technology, Beaverton, Ore. Contact (503) 672-8800 or www.fluence.com.

Simulation tool family The Active-HDL 3.5 family of tools (Standard, Plus, and Expert) offers several services including VHDL simulation and testing and designing FPGA and ASIC designs. The Active-HDL (standard edition) provides the FPGA customer with a fully compliant IEEE 1076-87/93 VHDL simulator that can be bolted on to any IC vendor's "ready-to-use" design flow. Active-HDL Plus and Expert Editions provide design environments capable of many services including managing and simulating complex FPGA and ASIC designs. The product includes an HDL editor, block diagram editor, state machine editor, automatic test bench generation, IEEE 1076-87/93 VHDL simulator, design manager, and structural simulation supporting VITAL 3.0, SDF, and EDIF. It offers a Windows-based, HDL design entry and verification environment for all levels of ASIC, FPGA, and PLD designers. Active-HDL 3.5 pricing starts at $3,600 for the standard edition, $5,200 for the plus edition and $12,500 for the expert edition. All prices include a 12-month maintenance contract. Aldec, Henderson, Nev. Contact (800) 487-8743 or www.aldec.com.

Design tool suite , Classic-SC automated transistor layout tool (ATL) v1999-1 is a new software release for design reuse and overall library layout development. Included within the release are two new placement and routing features: SC-Turbo and GDSII Import. SC-Turbo adds two capabilities to simplify design reuse and improve layout quality. This option provides cloning and user-defined pattern (UDP) capabilities to cell designers, simplifying design reuse and improving layout quality. GDSII Import leverages cell designers' expertise and use of existing cell layouts. This release includes a compactor that accurately handles 45-degree geometries for improved design density. A new graphical browser simplifies analysis of compaction results by providing visual layout data to the designer. By simultaneously considering constraints in both X and Y dimensions, 2-D compaction automatically converges to DRC-correct layouts. Terms of compaction constraints and design objectives are displayed to the designer in a graphical browsing format. The new v1999-1 features in the ATL flow include an improved capability to place large standard cells as well as the ability to create layouts from a Spice netlist. The cell router also supports the automatic creation of 45-degree wires to connect the placed MOSFETs. Since designers define their own netlist patterns for Classic-SC, the patterns can be used to extend or customize the placement of ATL. The v1999-1 release is available with list price starting at $240,000. The SC-Turbo and GDSII Import options are priced at $50,000 each. Cadabra Design Automation, Inc., Santa Clara, Calif. Contact (408) 982-9446 or www.cadabradesign.com

Embedded memory tool Embed-It! is a tool suite for embedded memory design and reuse in system-on-a-chip (SOC) applications. The suite is comprised of two new software tools--Embed-It! Architect for memory developers and Embed-It!
Integrator for system IC integrators--that address needs for reliable methods of authoring, licensing, and reusing a new generation of memory cores. The architect tool allows a company to build on memory-cell technology to create compilers that can be reused across different designs and process technologies. The integrator tool allows system IC integrators to rapidly generate hundreds of memory-core configurations with a proven-path to silicon. The suite operates within EDA environments and includes plug-ins for Dracula LVS/DRC from Cadence, Arcadia LPE from Synopsys, and Calibre from Mentor. The tool suite is shipped with a sample database. Embed-It! Architect is priced at $160,000 per year for each single, node-locked license and is renewable on an annual basis. Embed-It! Integrator is available in two options: $4,500 per year for each single, node-locked license for front-end views; and $40,000 per year for each single, node-locked license for front-end views and GDS. Virage Logic, Fremont, Calif. Contact (510) 360-8000 or www.viragelogic.com

Modeling tool Cellrater PCX enables designers to generate power models for use with synthesis and power analysis tools during development of complex electronic devices. It automates the process of power characterization and model generation for standard cells. The product characterizes a variety of cell types, including combinatorial cells, complex sequential cells, and I/O cells. Cellrater PCX generates a set of models, including state-dependent power and path-dependent power, leakage power, switching power, internal power (both hidden and transition components), and total power. The resulting power estimates are typically within three percent of Spice. Cellrater PCX generates Synopsys's Liberty power libraries, so it fits into existing synthesis and power analysis flows. Cellrater PCX is available on Sun Solaris. Pricing starts at $58,000 for a single floating license. Silicon Metrics, Austin, Tex. Contact (888) 828-3736 or www.siliconmetrics.com

Synthesis and Simulation Designdirect Vista software is an HDL-independent synthesis and simulation tool suite. The Vista package includes shrink-wrapped flows by the Leonardospectrum synthesis tool and Modelsim. Extensive benchmarking was conducted using a variety of designs to baseline the performance of the combined Leonardospectrum synthesis tool and the Designdirect core software. These benchmarks consisted of typical data path and control functions that customers tend to implement in high density CPLDs. Vantis developed reference designs and actual customer designs. The synthesis results were optimized for the Mach architecture and the core software characteristics and capabilities. Additionally, the Vista package includes a specially developed version of Modelsim simulator, which allows engineers to simulate the design based on system level VHDL and Verilog specifications, thus increasing the likelihood that the entire system functions as intended, the first time. Exclusive-OR factoring was added to improve arithmetic logic. Enhanced user controls were added for fitting legacy designs where pin placement is an issue, eliminating the need to respin the board and maintaining the Pinlocking attributes of the Mach architecture. Designdirect Vista software is designed as an extendable software suite. Designdirect Vista is available on Windows 95, 98, and NT platforms for $1,495. Vantis, Sunnyvale, Calif. Contact (408) 732-0555 or www.vantis.com

Compiler and run-time analysis D-CC, D-C++, and Fastj compiler suites and run-time analysis tools are available for Motorola's next-generation Version 4 (V4) Coldfire 32-bit processor core. The D-CC and D-C++ compiler suites work with all leading Coldfire development environments and debug tools. The Fastj compiler suite for V4 Coldfire core compiles Java source code directly to native Coldfire machine code. By eschewing the need for a Java Virtual Machine (JVM) in the target system, Fastj offers Java performance and code size comparable to C++. The V4 Coldfire core is a new superscalar 32-bit processor core for high-performance embedded applications. Providing over 3x the performance of the Coldfire 5307, the V4 core delivers over 250 Dhrystone 2.1 MIPS at 166 MHz. Enhancements in the V4 include new instructions to improve code density and performance, improved debug capability and an advanced branch prediction scheme to improve pipeline usage. The V4 core maintains complete upward code compatibility with existing Coldfire cores and also provides a cost-reduced migration path for higher performance 68K-based designs. Power Compiling Solutions for the V4 Coldfire core consist of an ANSI compliant, highly optimizing C, C++, and Java compilers, assembler, linker, program checker, block counter optimized libraries, and other utilities. The RTA Suite is available as an option. Supported host platforms include: Windows 95, 98, and NT; Solaris; and HP-UX. Pricing for complete Compiler+RTA tool suites start at $2,650 for a single user node-locked license. Compiler suites without RTA start at $2,200 for a single user node-locked license. Diab Data, Foster City, Calif. Contact (650) 571-1700 or www.ddi.com

Verification tool suite Suresolve, an automatic RTL test generation tool and Surecov, an automatic code coverage and Finite State Machine (FSM) tool, both form new versions of a functional verification and code coverage analysis suite that supports the Linux operating system. Product enhancements to Suresolve include directed test generation from the graphical user interface, while Surecov offers coverage utilities for checkpointing, start time, and test ranking, as well as additional Finite State Machine (FSM) analysis. Surecov's new coverage utilities include coverage start time for the designer to designate when coverage should start during simulation. Coverage checkpointing gives the designer the ability to look at coverage during the simulation run. Test ranking takes coverage analysis results for multiple tests and ranks these tests to optimize testing efficiency. Together these utilities allow engineers to evaluate the efficiency of individual tests versus simulation time and to rank multiple tests by coverage and run time metrics. Its FSM analysis now identifies parallel state transitions and lets the designer filter out implied reset transitions in state machines, if desired. The products are available for Linux, Windows NT, Sun OS and Solaris, and HP-UX. Sold separately, Suresolve is priced at $55,000 and Surecov is priced from $15,000. A bundled solution is priced from $65,000. Surefire Verification, Campbell, Calif. Contact (408) 374-4100 or www.surefirev.com

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