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Cells, Not Place-and-Route Tools, Now Determine Chip Density To optimize layouts, IC designers need to turn their focus from the place-and-route tools to the cells that really determine the density, as well as the speed and power consumption, of a circuit. by Emil Girczyc

The ability of place-and-route tools to position and connect cells on a die has historically determined the density of cell-based ICs. In the past, limited routing resources prevented ICs from being routed in the minimum area. In a single-metal process, all routing is performed in channels inserted between rows of cells. Signals that need to cross a row of cells are routed by inserting a space between adjacent cells. In two- and three-layer metal processes, though, over-the-cell routing became possible. However, the amount of routing available was typically insufficient to complete all routes, and routing channels were still inserted between rows of cells to complete the design. The advent of cell porosity allowed paths for signals to cross a row of cells without having to insert spaces between cells in the row.

In 0.18- and 0.25-µm processes, four or five layers of metal is the norm. Place-and-route tools now have sufficient resources to connect the cells as required with over-the-cell routing. Routing channels no longer need to be inserted.

Thus the density of standard cells, embedded memories, and hard macros now determine the density of core-limited circuit layouts. With the trend toward flip-chip and other packaging technologies that allow pads in the circuit interior, we will no longer have pad-limited designs; all chips will be core-limited.

Without spaces inserted to complete the routing, the cells abut in all directions, and circuit area is thus equal to the sum of cell area. Efficient cell architectures and layout techniques ensure efficient utilization of area within the cell, which minimizes cell dimensions. A 10 percent reduction in average cell area (weighted by cell utilization frequency) results in a 10 percent reduction in circuit area, which in turn results in 10 percent shorter routes, meaning lower power usage and faster circuit operation.

Standard-cell density typically conjures images of a good layout engineer pushing polygons to squeeze out every micron of space in a layout. In actuality, the cell architecture and cell set have a greater impact on circuit density.

The cell architecture defines those characteristics common to all cells in a library that enable them to be properly placed and routed. They include such features as routing pitch, cell height, power rail location and width, well height, and port location and style. The cell architecture affects the amount of white space within the cells and must be matched to the netlist and transistor sizes of the library. For example, tall-grid-height architectures make it easy to route large netlists but leave some empty space above and below small transistors. Small-grid-height architectures force wide transistors to be folded, thus increasing cell width, and may require the use of metal 2 routing. A good cell architecture has a height that balances such factors to minimize total cell area that's, again, weighted by cell utilization.

Further, good cell architectures ensure that the circuit can be routed without inserting any additional space between cells. The ports on the cells have multiple hit points and sufficient access from different directions and on multiple layers to ensure that all routes can be completed over the cell. Proper port placement maximizes the porosity for signals to cross the cell row in metal 2.

The cell set affects circuit density by making cells available that more efficiently implement common logic functions and drive strengths. Designers can increase performance and density by adding 20 to 30 new cells to their library specifically for the circuit or application and by tuning the available drive strengths of common logic functions.

So designers need to add the place and route's successor to their cadre of tools, turning to automated transistor layout (ATL). ATL enables them to quickly create rich cell libraries and add circuit-specific cells to existing libraries. Further, with ATL, they can rapidly explore alternatives to develop the best architecture for each library--maximizing cell density and routability and thus maximizing circuit density.

Emil Girczyc is the vice president of marketing at Cadabra Design Technology, Inc. in Santa Clara, Calif. He previously spent eight years at Synopsys, most recently serving as vice president and general manager of the design verification business unit.

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integrated system design  January 1999