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Take the High(-Level) Road to Fast Verification of Complex ASICs By following technology's leading edge, ASIC designers can catch bugs early, ease integration, and slash the length and number of their simulation runs. by John Perry

When it comes to verifying complex ASICs, and especially systems on a chip, conventional simulation tools and methodologies are failing designers. If it takes three weeks to verify a 500,000-gate design using simulation, and each bug fixed incurs another simulation cycle, something has to give. Usually the product schedule suffers, along with the resources and collective sanity of the verification team. Worse, with IC capacity soaring, ever larger delays loom.

The problem arises when designers wait until they complete all or most of a design before synthesizing it to--and attempting to verify it at--the gate level. At that point, the massive circuit complexity simply overwhelms today's simulation tools. What's more, verification at the netlist stage adds to the designers' woes when they must trace bugs back to the errant source code statement, in spite of limited visibility for completing such a task.

In short, today's most common design verification methodology has no future. Designers who ignore the call to change will lock themselves out of ASIC technology's leading edge. Instead of waiting to complete all or most of their circuits before verifying them, designers must adopt a flow that lets them assemble their circuits with confidence from preverified functional blocks--a practice that lends itself to emerging design, or IP, reuse strategies.

Designers willing to change their ways can wield new verification tools that supplement more common test bench tools--like simulators and test vector generators--to perform code coverage, test suite optimization, and state machine analysis. By changing their methodology to accommodate the tools, designers can make deep cuts in verification time, which often accounts for half or more of a large chip's design.

What do the supplementary tools do? Code coverage analysis of Verilog or VHDL functional blocks assures the designer that the applied test cases fully exercise the circuit. Coverage tools for verification, as offshoots of software coverage tools that programmers routinely use to check code, highlight unexecuted HDL code and indicate areas of a circuit that aren't exercised. Using the tools during test case development--especially if they can work across hierarchical levels--a designer can ensure that the verification process executes all HDL statements and branches, tests all expressions, toggles all variables, and exercises all paths through conditional statements and that a circuit's state machines advance through all states.

A second tool, a test suite analyzer, extends the concept of code coverage analysis to planning and managing a regression test suite, letting the designer view either the total or incremental test coverage of system or regression suites. Thus it can help to optimize regression suites to run the most productive tests first, while deleting redundant or unnecessary test cases. In addition, test suite analysis finds those cases that check specific blocks of code, thus improving verification efficiency following a bug fix or design change. It also lets designers quickly develop short but high-coverage regression suites for daily and weekly regression runs.

For circuits that employ multiple finite state machines, a state machine analysis tool lets a designer know if the states are tested, flagging occurrences of missed transitions and unexecuted input conditions as well as detecting key sequences. Such capabilities are important because verifying state machine tests--which tend to be handcrafted--is so difficult, particularly when multiple state machines interact.

Few engineers--indeed few people--embrace change willingly. But the signs are clear, at least for systems on a chip and other complex ASICs, that conventional test bench tools have run their course. A methodology modified to include code coverage and regression test optimization tools offers a practical, available, and effective alternative.

John Perry is the general manager of TransEDA, Inc. of Los Gatos, Calif. He was previously vice president of sales and marketing at Sand Microelectronics, where he helped set up the intellectual property market. Before joining Sand, he held senior sales and marketing management positions at Cadence Design Systems, Vantage, and Texas Instruments.

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integrated system design  April 1999