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Verification--Just How Much Is Enough? Providers of verification technologies must pick up the pace of innovation or risk falling further behind advances in process technologies. Design teams should weigh the new methods carefully. by Steve Wang

The design productivity gap between silicon capabilities and current verification solutions--simulation, emulation, and acceleration--continues to widen. The industry needs verification technology that is superior to simulation and offers an improved price/performance ratio over emulation or accelerated software simulation. We must also address the need to verify both the hardware and software together.

SOC designs place great demands on functional verification, especially for large systems. As design reuse becomes an increasingly popular and necessary methodology, layout teams are assembling large array blocks more quickly, to meet their time-to-market window.

Current trends indicate that the use of RTL design representations for verification is becoming the norm, while gate-level verification is tapering off. At the same time, design groups are beginning to adopt new technologies and methods of performing system verification at the highest level possible. Some of these tools and techniques bridge the gap between recent advances in design and persistent limitations in verification.

Today, toolmakers are introducing or developing a number of advanced verification technologies. Ranging from efficient test-bench generation to accelerated simulation, the tools promote verification at the RTL level or above. In addition, designers and ASIC vendors are progressing toward a separation of functional and timing simulations, further reducing the need to perform gate-level verification. However, even with these advanced techniques, designers are still facing intense pressure to obtain the highest verification throughput. Often they are willing to risk early adoption of new verification technologies just to sustain a competitive edge.

How can we pick winning verification technologies? Our customers believe that the highest return on their investment comes from tools that fit directly into their methodology. Investments in tools that require a design style change take longer to recoup, and often yield an unpredictable payoff. New tools must clearly demonstrate performance, quality, or efficiency, and should be unintrusive and easy to use, requiring little support.

When is verification complete? Companies address this issue quite differently, ranging from those who adhere to strict deadlines to those who desire to correct all problems irrespective of time constraints. A growing consensus in the industry suggests that the ability of the system design software to simulate true circuit behavior may provide the ultimate criterion for deciding when the verification process is complete.

The current commercial offerings, including several compiled simulators running on multiple workstations, can't achieve the performance needed to execute such a thorough system simulation run. Hardware emulation offers the best hope for running actual system software on a circuit under development.

However, setup and debugging challenges--and the high price tag--have so far kept emulation out of the mainstream. In the meantime, new verification technologies must attempt to improve simulation throughput by orders of magnitude while preserving the native simulation and debugging environment. One example of such verification technology is hardware in the form of a reconfigurable computing (RCC) engine based on FPGAs. The RCC engine configures its custom computing elements specifically for each design function. The design team enjoys the option of actually running system software in a hardware simulation environment. Rather than relying on short tests to verify specific units, this new simulation technology can perform longer tests to diagnose all possible combinations in the design.

Today, toolmakers are rapidly developing and introducing new technologies. Before committing to any new technique, however, users must take care to review its demonstrated value, ease of use, and ability to integrate into the current verification and design flow. In other words, before embracing a new technology, users should confirm measurable benefits in performance, quality, and efficiency. Any new verification technology that meets these conditions will certainly narrow the design productivity gap between silicon capabilities and current verification solutions. Such a product offers the best hope to SOC designers who need better ways to verify their systems before committing to silicon.

Steve Wang is cofounder and vice president of marketing at Axis Systems, Inc. of Sunnyvale. He was cofounder and vice president of engineering at Precedence and a system verification architect at Sun Microsystems.

To voice an opinion on this or any Integrated System Design article, please email your message to jeff@isdmag.com.

integrated system design  May 1999