The Deep-Submicron Neighborhood Demands Noise Abatement

No question--managing area, timing, and power is critical to the production of successful ultra-deep submicron designs. But none of that matters much if the chips are too noisy to work properly.

by Charlie Huang

Lower and lower yields have become an unfortunate albeit accepted reality as designers migrate to ultra-deep-submicron (UDSM) IC geometries. We now skirt a barely acceptable tradeoff between the improved chip performance and area reduction gained from utilizing UDSM and the cost of wasted silicon. The prospect of lower yields is keeping the brakes on the wide adoption of new process technologies. While many believe that the decrease in yield is a by-product of the increased complexity of the manufacturing process, a major culprit of low yields is actually the lack of noise immunity. Currently, the responsibility for noise validation resides with the product engineer after the design is complete. To stem the squandering of silicon, the responsibility for noise analysis must pass from the product engineer to the design engineer. Design teams must manage noise immunity throughout the design process with the same care that they apply to other design metrics such as area, timing, and power.

Previously, only analog designers concerned themselves with noise immunity. Now digital designers must worry over increasing transistor counts, shorter gate lengths, shrinking interconnect pitch, and higher clock frequencies, all contributing to the increased noisiness. In this age of system on a chip die sizes have remained relatively constant as designers cram more and more functionality onto a single chip. Consequently, average wire length has remained relatively constant despite the decreasing pitch. Scaling threshold voltages have also made digital designs more sensitive to noise. The net effect for UDSM designs is a much higher incidence of on-chip noise and lower noise immunity.

Noise in UDSM circuits can come from many different sources. In digital circuits the most damaging noise sources are crosstalk between adjacent switching wires, charge redistribution in static and dynamic logic gates, and supply fluctuations. Mixed-signal designs suffer from noise coupled into the substrate, interfering with sensitive analog circuitry. This noise originates from digital circuits that inject current into the substrate via their bulk terminals or from ground bounce on the power supply transmitted via substrate contacts.

Noise can significantly degrade a chip's operation, sometimes to the point of complete failure. Unfortunately, because noise problems often occur sporadically, requiring a particular vector sequence at a particular process corner and operating condition, they are often misdiagnosed as manufacturing defects.

Until now, the lack of decent noise analysis tools has justified the postponement of noise analysis until after design completion. Without reliable tools, designers resort to guard banding, or trial and error. Neither method is effective. Guard banding increases cost, area, and power while reducing performance. Using a tester to isolate and debug elusive noise problems can take many months and can also seriously lengthen time-to-market.

To increase a design's noise immunity, the team must expose design weaknesses by analyzing the effect of noise. However, the analog designer's method of analyzing noise via circuit simulation isn't viable for today's multimillion-transistor designs. Designers must perform noise analysis statically to verify that a design will function despite the presence of noise.

It's also insufficient to use DC noise peaks as a measure of noise immunity. This method yields a lot of spurious errors while potentially omitting real errors, because digital circuits act as low-pass filters that can reject tall, sharp noise spikes while passing low, shallow spikes that may cause failures. Since amplified noise can easily propagate throughout the chip with devastating effect, a much better noise metric is to ensure that no digital circuit will ever amplify noise.

Crossing the UDSM yield chasm requires us to bridge the gap between design and technology. We have to manage the impact of noise throughout the design process. We must possess tools that can accurately predict the effect of noise on a design, and employ a design methodology that understands the delicate tradeoffs involved. We can thus assure noise immunity without seriously harming other important design metrics.

Charlie Huang is the CEO and cofounder of Cadmos Design Technology, Inc. He previously served as the vice president of R&D of the Epic Technology Group of Synopsys. At Epic he developed PowerMill and subsequently PathMill. He holds a US patent on piecewise linear event-driven simulation.

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