packaging

Packaging Design for High-Performance ICs The high-speed signals in today's ICs won't reach the PCB if early parts of the design cycle don't address packaging design. by Wayne Nunn

Today's ICs are forcing changes in the package design process. The large I/O counts result in much more complex chip-to-package interconnect routing. At the same time, higher clock speeds and fast rise times have the potential to create high-speed transmission line effects on the interconnect, with cross-talk and electromagnetic interference reducing overall performance.

To address those issues and realize good performance from the packaged IC, package design is becoming a new discipline in its own right. Package designers must understand electrical issues and be able to explore the interaction between the chip and the package. Simultaneously, they must learn how to use more complex EDA software, so that they can adhere to physical and electrical design rules.

Package design is becoming less a drafting and assembly function and more an integral part of the IC and system design process. By specifically targeting it as a multifaceted engineering discipline, and by integrating advanced packaging software into the chip and system design flow, designers can improve design turnaround while meeting the challenges of wire-bonded and flip-chip substrate technologies.

The design process at VLSI Technology had to change to accommodate the new challenges. Traditionally, our typical process for packaging a new IC was to sketch a design in AutoCAD showing the chip location and the interconnect and send the drawing to an independent substrate supplier or packaging vendor (see Figure 1). The vendor would re-create the drawings using its own CAD tools and send Gerber plots or AutoCAD files back to us for approval.

That approach worked fine for lead-frame package designs, and for a while it worked even with relatively simple, low-pin-count BGA devices--as long as we required only a few designs a year. However, with the new generation of VLSI products, the process began to break down under the combined demands of increasing volume and complexity (see "Why Advanced IC Packaging?"). In order to offer a variety of package options for each IC, we needed to push through more package designs in less time. At the same time, higher pin counts and the need to optimize electrical performance increased the complexity of the drawings.

Design queues lengthened as we sent more jobs to the contractor. It became increasingly difficult to communicate design specifications to a remote vendor using sketches alone--sometimes the subcontractor wouldn't understand why we wanted a certain layout and would change it for the worse. For example, they'd route for continuity using a functionally incorrect approach. We'd then have to review why we wanted a particular layout, make corrections, and send the design back to the vendor for rework. The vendor often misunderstood our hand-drawn corrections, adding yet another correction cycle and delay. Thus the turnaround time from initial package sketch to final drawings became too long.

Figure 1	Traditional design flow
As the design enters the queue, the design process used for lead-frame IC packages begins to break down under the demands of increasing volume and complexity of high-I/O, high-speed chips in advanced packages.

The old approach not only reduced efficiency by increasing the time spent reviewing and correcting designs, but tended to produce suboptimal designs as well. We realized that we needed more control over the design process to minimize design time, optimize chip and package performance, and maximize manufacturing yields. Thus we decided to bring package design capabilities in-house and modify our design processes to address chip, package, and board design concurrently. The goal was to maximize performance by considering the IC and its package as a unified product from the outset, rather than treating package design as a back-end process. A growing number of other chip and systems suppliers are following that trend. Bringing substrate design in-house was thus a strategic decision that's leading us to reinvent our entire approach to packaging design.

In with the new

As we gained experience with advanced package design, we realized that traditional drafting tools and design methodologies had reached critical limits. Conventional drafting tools can produce lovely artwork, but they can't help the designer to adhere to electrical and physical design rules, and they don't allow us to extract data for modeling and analysis.

We realized that to optimize performance we would need software tools that offered electrical design and analysis capabilities for advanced packaging. We wanted tools that would provide in-house database accessibility; engage our manufacturing, assembly, and electrical characterization teams in the design process; and in the end produce camera-ready artwork for our substrate subcontractors.

We began to look for design automation tools that would allow us to design and analyze substrate interconnect expressly for the requirements of advanced packages. They include the ability for the package to support more functionality on the die. Some of the new parameters for the high-performance chips include multiple voltages requiring separate power planes, high speed I/O, differential pairs, impedance matching, and fixed impedances. In addition to the individual signal characteristics, the packages must support a larger number of other critical signals and I/O buses.

When it became time to choose a new packaging design tool set, we undertook a disciplined evaluation of the commercially available packaging design tools from several vendors. We developed a formal "review requirements" document examining nearly 100 criteria and then decided on our most critical needs:

1. The ability to start a design with or without a netlist: For single-chip designs, it's usually more efficient to start without a netlist and focus on routing for highest density and electrical performance, then create the actual chip-to-pin netlist from the considerations. On the other hand, few chip packages require working with a predefined netlist.

2. The ability to build hierarchical libraries containing "components" unique to BGA design: For example, BGA pads, staircase via stacks, bond fingers and fiducials, and even array patterns and trace routing patterns for escaping from flip-chip pads.

3. Interactive and automatic routers that can achieve very high trace density: The devices generally can route at any angle, "push" other traces out of the way while routing, and automatically adhere to BGA design rules.

4. Automatic bond finger generation: Manually creating bond fingers that meet manufacturing requirements is a tedious and exacting process.

5. Integrated design and manufacturing rule checking (DRC): Integrated rule checking facilitates first-order electrical analysis, thermal analysis, and manufacturing verification during the design process.

6. Integration of best-in-class analysis software into the design process: Best-in-class analysis tools should be integrated into the design process for detailed analysis and characterization.

7. The ability to import and export data in our most commonly used formats: To be truly useful, the tool must support the data formats we use in other parts of the design process, such as DXF, GDS II, and Gerber.

Figure 2	BGA tools support greater design density
IC package design software needs integrated analysis capabilities and high-density routing based on a radial approach rather than an orthogonal one, allowing a larger number of connections in a smaller space.

For the benchmark we chose a highly complex single-chip BGA package based on an already executed chip design. That selection gave us the ability to compare the performance of the candidate tools with our existing environment and techniques. After testing products from several leading EDA vendors, we chose Encore software from Xynetix Design Systems in Rochester, N.Y. We liked Encore's look and feel, its built-in "intelligence," and the fact that it was specifically designed for single-chip and few-chip packages. The tool also offered an open environment and the ability to integrate analysis into the design process.

High-fashion interconnect modeling

A key factor in our selection criteria was the ability to create package interconnect models for our internal and external customers, who need package models to perform circuit simulations at the chip and system levels. To that end, VLSI has been working with both Xynetix and Ansoft Corp. in Pittsburgh to integrate Ansoft's 2D and 3D parametric extraction tools into the Encore design environment.

The integration will allow engineers to kick off the analysis tool from within Encore--an option more convenient than having to switch between the design and analysis environments--and will make it easier to set up and use the analysis tools. The engineers can select nets by group, net class, or individual, and then automatically extract all interconnect features including bondwires and BGA balls. The Ansoft tool uses the layout data from Encore and builds a 3D model of the interconnect (see Figure 2), which is then used to generate the RLC matrix. The parasitic values then help in generating a Spice model for system simulation. The integration is currently in beta testing, and the open architecture promises to make it easy for us to add other analysis tools as needed.

Toward a streamlined process

So far, Encore has proven itself capable of meeting our needs. We completed a 596-ball four-layer design as a training exercise and are currently fabricating our second design--a four-layer EPBGA with approximately 700 balls, a 1-mm pitch, and multiple voltage partitions. Both designs have made use of the tool's automatic wire bonding capabilities. We're now working on a flip-chip design of 1160 balls and a 1-mm pitch, as well as a multilayer buildup technology that requires creation of very complex via structures.

Using Encore, we expect a much more streamlined design flow that eliminates the need for the subcontractor to reenter our designs as well as the multiple review and correction cycles. We're also able to optimize the performance of the packaged chip by analyzing the designs before sending them to the vendor (see Figure 3).

Note that AutoCAD remains an important part of our design process. It's a good drafting tool that has deservedly become the industry standard. We use it to import a vendor's existing AutoCAD drawings and generate fabrication and assembly drawings. Encore reads the DXF data directly and converts it to "intelligent" data that we can manipulate within Encore. The arrangement lets us perform DRC verification, make design changes to optimize performance, and then transfer the design back to AutoCAD using the DXF format.

Figure 3	Improved design flow
The streamlined advanced IC package design flow eliminates delays caused by outsourcing critical design activities.

Though the new design tools allow us to optimize package designs for performance and manufacturability, they also require new thinking and skills on the part of the package designer.

Encore automates many of the processes--such as filleting pads and vias automatically during routing--that are needed to create good, manufacturable designs. Automation saves a great deal of time and improves results. But one of the tool's primary advantages--the ability to manage electrical effects and follow design rules--covers ground new to package designers whose prior experience consists mainly of using AutoCAD for lead-frame designs. The learning curve steepens at that point, since we must include not just tool training, but training in general design and layout techniques for managing electrical effects as well. Nonetheless, it's a process change that we must make in order to achieve the results we want with our new-generation ICs.

A more far-reaching process change is our effort to incorporate packaging design as an integral element of the overall chip design process. The tool's open architecture will aid the integration by allowing design teams to predict how packaging decisions affect overall device and system performance. The tool provides manufacturing links, back-end verification, electrical and thermal analysis, and direct access to other tools via an "adviser backplane" that monitors our design decisions as we proceed. The backplane lets us examine electrical, thermal, manufacturing, and system-level design parameters prior to actual tape-out. As a result, the tool can help optimize design performance while avoiding delays and reducing the number of iterations between the design and manufacturing departments.

EDA tools have been shown to greatly advance the speedy design and delivery of packaging solutions for deep-submicron devices. We've set an internal goal to turn around completed designs, optimized for electrical performance, in two weeks. We believe that such a goal is realistic, but only by augmenting existing procedures with leading-edge EDA technology.

Wayne Nunn is a staff packaging engineer at VLSI Technology, Inc., in San Jose. He focuses on design automation software and methodologies for advanced packaging design, drawing on 25 years of experience at VLSI and Digital Equipment Corp.

To voice an opinion on this or any Integrated System Design article, please email your message to miker@isdmag.com.

integrated system design  January 1999