Over the years, market research has indicated that users of hearing-instruments consistently stress the importance of hearing and comprehension while in a noisy environment as their top priority. Unfortunately, that attribute continues to be the weakest performance point of most products currently on the market.

Based in Stafa, Switzerland, the Phonak Group specializes in the development, production, and global distribution of advanced hearing systems. The company's goal is to correct impairments in the complex human sensory organ and to create products whose performance comes close to that of the healthy ear. To address product enhancement, Phonak launched an intensive three-year research and development program to address the problem. As one step in the strategy, Phonak created a highly sophisticated and complex system that it calls Digital Perception Processing.

The new system represented the company's shift from an analog to a digital signal-processing platform for hearing instruments. The size, power, and function requirements needed for the transition dictated that Phonak should develop its own digital-signal processing core and integrate as much functionality into a single chip as possible. Built around 0.25-ým technology, the chip architecture has been designed to serve as the basis for new products for years to come. As a result of the program, the company is now able to fully integrate pyscho-acoustic perception models of the ear and to simulate the functions of 20 critical audio-frequency bands in the inner ear — thus providing an extremely natural hearing experience.

Channeling challenges

Along the way, the company has developed several standards including Audiozoom technology, which uses two microphones to enable the listener to concentrate on a particular signal or speech source while dampening background noise. Hearing programs can be selected by a remote control to enhance hearing and understanding in real-life situations. The company has also developed the Microlink wireless communication system, which provides frequency modulation technology for hearing instruments. Discrete high-performance microphones eliminate ambient noise as voice and signals are registered directly at the source and transmitted to a tiny radio receiver, which can be snapped into many behind-the-ear hearing instruments (see Figure 1).

Phonak's new technology has been incorporated into a family of products known as Claro, which the company describes as the first communication/hearing computer that actually "listens." Designing the technology for Claro presented a complex problem: how to build chips that incorporate myriad functions in a small area while still minimizing power requirements for the complete system. Since the digital domain allows for more sophisticated designs than traditional strategies, Phonak didn't want to simply transfer its legacy analog designs onto a digital format.

The first generation of Claro technology design included microphones, a remote-control receiver, a set of three chips, passive components, and a loudspeaker. The digital functions of the hearing instruments were integrated into a 200,000-gate system-on-a-chip (SOC). The chip included substantial digital-signal processing power plus a microcontroller to load various filter sets and to control system functions, RAM, ROM, and a D/A converter. A second chip integrated the A/D converters as well as the time-base and power-management circuitry — and was bonded to the main IC. A standard EEPROM stores non-volatile parametric data for the programmable algorithms. These parameters allow the hearing instruments to be adjusted for individual users.

The entire device had to be packaged into an area small enough to fit into the human ear canal (see Figure 2). Consequently, the die size for the SOC couldn't exceed 20 mm2. Since hearing aids are battery powered, the maximum supply current was a 1.5 mA, with an operating voltage range of 1 to 1.5 V and an operating frequency of 2.5 MHz. Finally, because the instrument used a series of complex algorithms such as multiband compression, spectral subtraction, and Fast Fourier Transforms to fulfill the functional requirements, the instrument required a 130-MOPS throughput.

The performance requirements for the digital sections demanded a high-performance digital-signal processor (DSP). We couldn't use a general-purpose DSP core because even the most advanced low-power DSP cores have power requirements that exceed the Phonak specification by a factor of ten. The relatively high throughput requirements might suggest using multiple DSP cores running at very low frequencies to minimize power requirements. However, this approach would not only exceed the power constraints, but would require too much area as well. The only option was to create a proprietary DSP core that embodied the necessary digital algorithms.

Innovating with SOC

The increased size and complexity of designing highly integrated ICs, coupled with compressed design times, has led many companies to rethink their traditional design processes. To increase the chance of success on the first attempt, we had to develop a well-thought-out methodology that included all aspects of the design from concept to silicon.

Standard design processes are generally organized as a series of discrete stages beginning with algorithm and specification development, progressing through separate hardware and software design and prototype development phases, and finally to testing and verification. There are often separate paths for software and circuit development; consequently, after the initial specification is approved, changes are both difficult and risky. In addition, the engineering teams involved with each separate step of the process rarely share a single, unified view of the system under development.

Because of compressed design time cycles, codesign is now common; several design teams are responsible for the functional design of the DSP software, DSP hardware, controller hardware, and the physical chip design. Unlike the development of traditional ASICs, the new paradigm finds design teams working concurrently and design phases exhibiting large overlaps. The design flow, therefore, incorporates early consideration of verification and optimization at every design stage. Since SOCs represent a higher level of integration and include DSPs, microcontrollers, and other elements as well as complex software, any problems that may occur in the integration of the hardware and software represent a significant and major threat to the fulfillment of the next milestone.

Team redefined

The new design environment means engineers must find new ways to work together, often using new tools in different working environments. For example, tools mustn't only be able to specify complex SOCs: Ideally, design tools should be able to communicate specifications through the design process as well as successfully integrate with other tools. Yet the complexity of SOCs has made verification both difficult and time-consuming. Because recoding and testing designs can account for as much as 70 percent of the design process, designers must be able to work with models that have different levels of detail. They must facilitate the verification of individual blocks as well as the entire chip. Improper translation between tool sets aggravates the problems with the final system-level integration and increases verification difficulty.

Phonak engineers responded to these new conditions as they created and enhanced the Claro platform. Our new design flow employs codesign teams that develop the algorithms and hardware in parallel, working in conjunction with each other. The teams accelerate their work by using a common set of tools to design, simulate, and verify the high-level design. These tools, including Simulink, Matlab, Real-time Workshop, and xPC Target (from The Mathworks, Inc. of Natick, MA) help to accelerate the floating point algorithm development, to verify the algorithmic functions early in the design process, and to create a testing model that could be applied in each step of the design process.

To design the Claro technology, Phonak divided the process into three components. Phonak engineers were responsible for the high-level descriptions of the algorithms involved in the DSP core as well as the verification and testing of the algorithms. They also implemented the controller hardware around the CoolRISC core from Xemics and the controller software. As the DSP algorithms and architecture became more refined and robust, Frontier Design's (Leuven, Belgium) engineering team converted the resulting C code, which represented the algorithm, into a VHDL description of the DSP hardware.

We also turned to Xemics of Neuchatel, Switzerland, to supply the RAM, ROM, and CoolRISC microcontroller cores, as well, to integrate the various components into the SOC. Adding outside design teams this way helped with the schedules and with the design of some of the new technology — however, collaboration also required us to work closely and carefully with our partners to ensure compatibility and consistency in the design and implementation of the IC.

Assisting in sound design

While developing the first generation of Claro technology, Phonak engineers used Matlab which allowed the design team to focus on the development of the algorithms and not on correcting syntax-level errors. Since then, the company has upgraded to the latest version of the tool and added Simulink to model, simulate, and analyze dynamic systems. Other tools now allow engineers to add I/O blocks to Simulink block diagrams, generate code with Real-time Workshop, and download the code to a second PC that runs the xPC Target real-time kernel. These tools assist in rapid prototyping and hardware-in-the-loop testing of control and DSP systems by generating customizable code from models and automatically building programs that can run in real time with existing simulation environments.

In the ongoing development of the Claro technology platform, Phonak engineers use Simulink, xPC Target, and Real-time Workshop to develop the floating-point algorithms that define the system's functions. Within this environment, engineers create a model of the system and then develop and test their algorithms using real-world data. To verify the functional behavior of the algorithms and its subparts, Phonak has developed a set of test programs in Matlab that run on a standard personal computer. Based on the results of the testing, the designer adjusts the block and lets the tools automatically revise and generate the new operating code.

Working in this fashion, all the algorithmic functions can be functionally verified while they are still in a floating-point format. Happily, the productivity increases have been dramatic. In the past, two seconds of real-time operation could take as much as one minute to simulate. In the current environment, Phonak engineers enjoy real-time rates for simulation.

It is extremely important, therefore, to know that algorithms are functionally correct before moving to subsequent stages in the design process. At the high level of modeling and algorithm development, the short simulation times permit rapid and thorough verification, whereas later stages of development take significantly longer due to the much longer simulation times. By working with Simulink, engineers know that the algorithms won't have to be functionally modified later.

After the engineers ensure that the design meets the specifications and goals, they perform overflow scaling. Overflow scaling includes, among other tasks, reducing the required dynamic range of the signals by appropriate mathematical operations without changing the underlying functional behavior and scaling the signal nodes and parameters to a fractional format. From that point, the engineers create a second, smaller equality test suite to ensure that this adapted algorithm version and all other subsequent versions down to the gate-level description correspond exactly to the high-level algorithms. Having a uniform test suite that can be used at every step in the design process eliminates one potential source of uncertainty should problems arise.

Parallel design activities

Floating point algorithms can't be used efficiently in low-power, small hardware implementations. The algorithms have to be converted into fixed-point data and arithmetic representations. In the current environment, the M-code is converted directly to a C++ add-on that supports bit-true data types. Unfortunately, we must translate the code manually, because the C-code output generated by Real-time Workshop has too much overhead to be compiled into VHDL and low-power implementations. The C code is then converted by Frontier Design's A/RT tool suite into an RTL VHDL description.

The A/RT tools synthesizes a VHDL processor architecture that consists of a dedicated data path and a microcoded VLIW controller. The tool optimizes the data path for the particular tasks it has to perform and assembles execution units such as an ALU, address calculation unit, ROM, RAM, registers, and multiplexers to perform the functions. The flexible exploration capabilities of A/RT enable a quick and optimal definition of the datapath elements, which is essential to come to an efficient implementation. We custom designed several special execution units to optimize the architecture.

We provided synthesizable VHDL output to Xemics for synthesis and integration with additional, third-party IP cores. Frontier Design and Xemics collaborate in the development of extremely low-power, low-voltage implementations of advanced DSP architectures and circuits to be implemented in SOCs. Frontier's role in the design process typically concludes with bit-accurate VHDL source code.

Frontier and Xemics also collaborated in building power and area estimates based on heuristic rules. Since this process occurred in parallel with the design process, they couldn't use accurate power estimators as the design was still in process and incomplete. Xemics combined data provided by Frontier with its own data to estimate power and area requirements based on the sizes, activity, and numbers of blocks. The actual power characteristics of the SOC were used to modify the heuristic model for the next-generation chip.

Figure 1 - Design Flow

Effective system development relies on efficient design flow. The move to digital audio device platforms dictated the streamlining of strategy.

The last word

Developments in DSPs are only one part of the equation needed to create improved hearing devices. While fully digital instruments represent a significant step forward in technology, Phonak research has shown that the inclusion of multi-microphones in the system significantly increases the user's ability to comprehend sound in a noise-laden environment — one of Phonak's primary goals. Consequently, Claro technology will continue to require increasingly complex systems within a small area using limited power.

The move to Simulink and its related products has allowed Phonak engineers to speed up the design cycle in two ways. First, modeling, developing, and testing algorithms using Simulink allowed our designers to create and verify the functions of the algorithms more quickly — and earlier in the design process. With help from Real-time Workshop and xPC Target, Simulink facilitated the push-button compilation into real-time capable code. Secondly, the process produces clear functional system specifications that could be used to guide downstream development.

We hope to make additional incremental improvement in the design process in the future. The Mathworks currently is working on challenges associated with moving from floating point algorithms to C code appropriate for low-power, small hardware implementations. Importantly as well, Phonak engineers plan to move the testing of algorithms from the current personal computer platform to a mobile unit. That change will allow engineers to actually field test algorithms in a range of real-world settings and eliminate the need to postpone field testing until late in the development.