If you're reading this, chances are that you're coming to Los Angeles in June to be part of DAC. If you're reading this, and you're not coming to DAC, think again. You'll be missing the biggest technical conference, carnival, and trade show in EDA. A great deal of the action in electronic design automation is on the West Coast. Subsequently — although the conference in New Orleans in 1999 was well-attended — this year's DAC on the West Coast promises an attendance that's lively, noisy, and huge. Professor Giovanni De Micheli (Stanford University's EECS department) is general chair of the conference this year and we couldn't be in better hands. De Micheli points out that we can expect the turn-out at this year's DAC to beat all previous records — not only is L.A. itself home to lots of designers, it's also only a short plane flight or lively road trip away from the center of the technical universe — Silicon Valley.

In addition to De Micheli, and undoubtedly out of respect to the Bay Area's cross-town rivalry, Professor Jan Rabaey (U.C. Berkeley's EECS Department) is providing leadership, as well, in his role as vice chair of the conference. Rabaey has been part of the EDA industry since the early days. (See ISD Magazine's interview with Hugo De Man and revisit Rabaey's early days at U.C. Berkeley with the likes of De Man, Pedersen, and Kuh — p. 86)

Lights, camera, action

DAC officially opens on Tuesday, June 6th at 9 AM, with a keynote address by Theo Claasen, executive vice president and CTO for Philips Semiconductors. In a reassuring change from last year's platform-specific opening keynote, Claasen's topic this year, "First-Time-Right Silicon, but to the Right Specification," promises to challenge his audience with a broad-based discussion of the design trends needed to meet the rigor and demands of system-on-a-chip (SOC) development — in particular, developing more finely tuned specifications for a design and moving the emphasis for design validation from simulation to "Silicon Systems Platforms" that eases the need for from-scratch development of these complex products.

Prior to the opening keynote, DAC chair De Micheli will formally welcome the attendant masses with his opening comments and presentations — various best paper awards, scholarships, professional accomplishment commendations, and the Phil Kaufman Award will be bestowed.

At the other end of the conference, Thursday's closing keynote on June 8th at 1 PM features this year's Kaufman Award winner, Professor Hugo De Man (Belgium's Katholieke University). De Man will outline the evolution of today's design focus away from personal computers and toward wearable computing products that will enhance global "connectivity." His thesis contends that designing for CPU architecture is a far different exercise than designing to small, robust, low-power, programmable-platform products, which include embedded cores and a mix of software and hardware IP. His is an appropriate close to this year's DAC and an indicator of what the future will hold for EDA vendors and their customers.

Scene 37, Take 1

The focus of DAC changes from year to year as the trends in EDA ebb and flow. This year — the 37th annual event — the hot topics in the industry can be clearly tracked by examining the titles and contents of the various special sessions and panels that have been assembled by the various DAC organizing committees.

Most obviously, DAC-week Wednesday has been designated as Embedded-Systems Day, expanding on last year's mini-track. Included in the agenda for the day is a mid-day panel endearingly entitled "Embedded Systems Design in the New Millennium." Chaired by Professor Richard Newton (Department of EECS, U.C. Berkeley), CEOs and CTOs from ARM, Infineon Technologies, Mentor Graphics, Broadcom, and Rambus will be discussing the business and engineering trends surrounding technologies at the center of design reuse, IP, and SOC advances. The participants — coming from a mix of EDA and systems houses — will engage in high-level discourse on refining applications, power versus performance trade-offs, and porting board-level system expertise to chip-level system designs.

In addition to the mid-day panel, other technical sessions of interest within the embedded focus on Wednesday include Sessions 18 and 19 on power analysis, optimization and compilation techniques, respectively. Papers at these sessions represent an international set of contributors from academia and industry. Sessions 23 and 24 move to system-level design considerations including modeling, synthesis, and verification for SOC development.

The walk of the stars

Where will the EDA vendors be challenged? Clearly in a variety of areas this year, and in the years to come, a number of issues are going to need addressing. According to De Micheli, the switch to system-level design is happening here and now — partly as a response to market demands for SOC-level integrations, which is in turn driven by research and development in shrinking geometries and increasing on-chip device counts. The move to system-level design will require higher levels of abstraction in the design flow. A lot of conversation from this past year about HDLs, OVI, VI, C, C++, and Java will all be revisited across various panels. Certainly, the panel during Session 25, "The Future of System Design Languages," will be a principle forum for the discussion. Participants include a range of EDA vendors and semiconductor companies — including Synopsys and TI — all proposing standards and/or design languages to help out with system-level design.

Meanwhile, timing closure is on everybody's minds these days — no denying it. Not only are the newer tools and methodologies clearly reflecting this problematic design challenge, the newest and potentially most interesting start-ups in the EDA space are making a lot of noise this year at DAC. Session 10 — a panel entitled, "Design Closure: Hope or Hype" — may be the hottest ticket in town on Tuesday morning. It will be a clash of titans (or titanettes) in the area of physical design and timing closure. (Check out your DAC program to see if you've guessed right as to who might be populating this panel.)

The designers basically have two choices. They can go with modifications and updates of the existing tools from established vendors and, in so doing, protect legacy investments in existing flows and the personnel that manipulate them — or, alternatively, they can go with the new kids on the block who are basically proposing that users throw out various amounts of existing tooling and methodologies to migrate to the newest in product offerings.

We will be privy to the range of opinions at DAC around hardware/software co-design. The value added to the system will depend on the embedded software according to many; as the industry moves to more re-configurable design styles, more tools will be needed to support software design. Various sessions have been organized around key aspects of co-design including Session 20, a panel discussing software versus hardware design issues related to SOC devices. This panel, as well, includes voices from both industry and academia.

Then there's low power — not surprisingly, a big problem for everybody in the communications industy. Your slim little cellular phone or wireless-enabled PDA needs to provide lots of capability while running on very little power and with very little heat dissipation — an interesting conundrum considering the amount of computational and memory oomph you've got to have on board to make your device really useful as you rush from here to there. Session 9 (Clock and Power Grid Analysis), Session 21 (Power Estimation and Performance Improvement), and Session 49 (Low Power Design Techniques) will all include technical papers addressing the issue.

Related, as well, to the phenomenal increase in global demand for all classes of wireless communication devices — the mixed-signal, signal integrity (noise), and RF challenges associated with these designs will be discussed in detail at Session 11 (RF Simulation), Session 14 (Signal Integrity), Session 26 (Mixed-signal Design), and Session 35 (a panel on Survival Strategies for Mixed-signal SOC) among others.

The envelope, please

And, say one was daring enough to ask Professor De Micheli what he will be attending at DAC — as his time allows — what would one hear? His answers are as interesting and as diverse as the topics being covered in the technical sessions. De Micheli would like to sit in on sessions on interconnect issues (Sessions 4 and 31), sessions exploring various challenges in design verification (Sessions 7, 12, and 16), and logic and physical co-design (Session 17) — among others.

Clearly, designers and tool developers should feel equally inclined to sample a range of offerings if they consider themselves committed to maintaining a broad perspective on issues within the field. And, since everyone knows that there's an embarrassment of riches when it comes to the topics available at DAC, that kind of "topic tasting" is easy. The classic subjects — interconnect, verification, logic/physical design — are augmented, not surprisingly, by sessions and panels discussing synthesis, the ever-evolving technologies surrounding test structures and design-for-test, as well as model checking, algorithm development, and floorplanning and placement. Take some time in examining the full offerings at the conference before settling on a plan of attack.

Gunfight at dot.com coral

There's this great gunfight going on between EDA and dot.com these days. Session 15, moderated by Jennifer Smith (Dain Rausher Wessels), continues a discussion currently underway in the EDA industry. Recent hiccups in the stock market have caused a quickening of the pulse across EDA sparking hopes that venture capitalists will revisit the investment opportunities offered by IC CAD-tool vendors. Meanwhile, and perhaps ironically, a number of EDA vendors are seriously re-evaluting their own business models to include some level of participation in e-commerce, be it through on-line licenses, enabling remote collaboration across (geographical) space and (design-life-cycle) time, or by joining in the supply chain samba line shaping up along the design and production flow (see "Inside EDA" on p. 18).

As a corollary to the discussion, panelists in Session 43 (Web-based Frameworks to Enable CAD R&D) will cover the non-trivial technical details of sharing and coordinating design projects across the web.

Lastly, but not leastly, there's the drama surrounding the human resources shortage in EDA and elsewhere in chip-related engineering. This is not news to anybody in the industry, but the situation is quickly driving the whole recruitment and retention prospects for any particular company — particularly those companies in EDA — into condition red. The problem is particularly critical for the small EDA start-ups with few resource dollars to lure in young talent and, therefore, offering those elusive stock options as talent bait (for dreamers willing to believe that anyone in EDA is going to go public anytime soon.) Session 50 offers a panel entitled "Emerging Companies: Acquiring Minds Want to Know" and promises to cover the talent pool shortages and other intriguing issues unique to the world of EDA — including the mystique surrounding "start-up, sell-out, start-again. "Participants will include the CEOs of a number of small, but feisty, EDA companies including the legendary Joe Costello — now CEO of Barcelona Design. Don't plan to leave town before sitting in on this most fascinating and enigmatically scheduled session (Thursday afternoon at 4:30 PM).

And, if you're going to stay through late Thursday anyway, why not make your week complete by attending to your continuing education at one of the six excellent tutorials being offered on Friday, the 9th, from 8 AM through 5 PM. Presentations range from synthesis and layout, to static-timing analysis, system-level design, DSM signal integrity, wireless SOC technology, and low-power system design. Seating is limited at the tutorials, so register in advance!

The GUI Screen Actors Guild

Finally, don't forget the show floor — as if anybody could. Between the "talent" and the barkers and the demos and the give-aways, you actually might find time to try out a tool or two, check out a GUI, explore a little-known company and/or their product offerings, or get some hands-on exposure to the latest and greatest offerings in the EDA and peripheral industries.

In the end, the success of a trade show depends on what people take away with them and, more profoundly, whether positive and appropriate shifts in technology trends have been initiated. Sometimes, we hear from industry that DAC has grown too big for it's own good — that the showmanship has overwhelmed the conversation and exchange of ideas. We will leave it up to those in attendance in L.A. to decide for themselves. At this point, however, we continue to endorse and celebrate DAC as a unique venue for technical interchange as well as an important — but not easily quantified — opportunity to build community across the EDA and designer/user populations.