The demise of full-custom IC design has been prophesied for years. The theory states that once ASIC design tools reach a certain level of maturity and performance, full-custom design will wither away from lack of demand. From that point on, the argument promises, IC design will become synonymous with ASIC design.

The progress of ASIC design in the past decade would seem to support this view. There is no disputing the fact that the quality of ASIC design has improved greatly, just as industry pundits predicted. Moreover, synthesis tools routinely generate mammoth system-on-a-chip (SOC) designs, and with such efficiency that no team of designers could possibly match the output. With such superlative results in creating todayýs ICs, itýs no wonder that the great majority of current designs are developed using ASIC tools.

So why is full-custom design still very much alive and being used throughout the electronics industry? The simple truth is that ASIC design tools generate circuits with inferior performance, power, and density capabilities compared with the full-custom approach. This is especially true as the design world pushes further into the realm of the deep submicron (DSM). Current ASIC design tools are still unable to leverage the regularity of data paths, switch arrays, and storage arrays in generating highly regular cell-placements. Any irregularity in such portions of the chip translates into wires and delays longer than needed and, consequently, a loss of performance and power.

The only way to efficiently negotiate complex chip-design is for ASIC tools to abstract the models upward several levels. Whereas the use of modeling languages with increasingly higher abstraction capability enables efficient high-level design capture and simulation, the corresponding synthesized circuits have an increasingly- larger number of cells whose optimal position and wiring significantly affect the circuit performance. The quest for a tight link between high-level modeling and layout has been the object of research for some time. Today new players in the EDA market, as well as traditional EDA providers, are proposing new tools and methodologies for physical design. Nevertheless, current tools are unable to beat custom design on regular structures.

So, one can cogently argue that there will always be a place for full-custom design due to the fact that ASIC design necessarily lags behind silicon capabilities. But letýs be clear here: Full-custom design will be limited to a small, but important, arena. Today, custom design is typically employed by those companies looking to get the highest performance, density, or power out of their designs. Examples include high-volume microprocessor designs and bleeding-edge telecommunication applications. Even in these situations, however, the use of full-custom design is restricted to optimizing only portions of the chip design.

For instance, a design group could start out using an ASIC flow to create the base design for a next-generation microprocessor. Then, the team could take key portions of the ICýperhaps the memory and the datapathýand adopt a full-custom design approach to fine-tune these critical sections. In another scenario, a communications- design group might decide to use full-custom techniques to create a parallel-to-serial converter for a high-speed switching system. The result would be a much faster converter than could possibly be produced with an ASIC approach.

Of course, not everyone agrees with this argument. In fact, the design community remains divided over the question of whether the gap between full-custom and ASIC designs can or will be closed.

What better place to continue that discussion than this yearýs Design Automation Conference (DAC) in Los Angeles? Weýve assembled a panel of talks to investigate the question of whether ASIC tools can ever come close to the performance and cost of true full-custom design. It promises to be an informative, lively, and sometimes heated debate that you wonýt want to miss.