With the introduction of HDTV, satellite dishes, and many fast Pentium microprocessors, one would think that the world is switching over completely to digital electronics. But that perception is far from reality. Increasingly complex consumer products, such as cellular phones with Internet capabilities and interactive televisions, continue to require analog interfaces. Engineers have come to rely on mixed-signal design solutions for these devices, in which both digital and analog functions are combined on the same chip. Typical mixed-signal systems today usually contain 80 to 98 percent digital functionality. A typical video processing system drives both the video and audio signal on a television (see Figure 1).

Accordingly, designers at Telecruz Technology, Inc. (San Jose) faced a challenge. In order to bring the TC702 to market (an interactive platform solution that allows television manufacturers to add Internet capabilities to televisions and set-top boxes), we needed to combine our mixed-signal intellectual property (IP) with an analog/mixed-signal RISC ASIC capable of powering the solution. This proved to be an easier concept to sketch out on paper than to realize in silicon. To resolve our development challenges, therefore, our engineers at Telecruz needed to find an ASIC vendor capable of meeting our complex design requirements.

The road to analog/mixed-signal design

Today, many silicon vendors offer mixed-signal capabilities to satisfy customer requirements. There exists a multitude of challenges in offering mixed-signal capability combined with pure digital design in ASICs. One of the key issues is that analog and digital circuitry require separate power supplies with different voltages. For example, Toshiba's 0.18-ým process technology requires different voltage for the digital versus the analog circuitry. The analog cells run at 2.5 V and the digital portion (logic cells) runs at 1.5 V (see Figure 2).

Engineers face an additional problem in that digital designs continue to run faster. The I/Os have to offer speeds compatible with these digital designs. For example, if the mixed-signal device is a digital-to-analog converter (DAC), then the settling time (the time needed for a digital input to convert to an analog output that is within a percentage of full-scale error) gets shorter as the chip runs faster. The same time constraints apply for analog-to-digital converters (ADC). The analog-to-digital conversion time needs to be much shorter as the chip runs faster. Otherwise, the ADC accuracy is affected and the analog signal quality is compromised.

Often the vendor has to offer capabilities within their latest silicon technology to match the speed requirements of the digital portion of the chip. For instance, the analog speed of the chip may be 33 MHz, which can be easily satisfied with 0.35-ým technology. On the other hand, the digital speed requirement may be 100 MHz, which forces the vendor to use 0.25-ým silicon technology.

Figure 1 - Stop, look, and listen

A typical video processing system drives both the video and audio signal on a television.

As a result, vendors continue to see analog/mixed-signal as a driving force in the design of many products in the market. Engineers and analysts alike can only speculate on when, or if, analog will be replaced completely; but until that time when various functionality issues and analog requirements are solved, analog/mixed-signal designs will continue to have a huge effect on the industry.

For engineers who develop analog/mixed-signal designs, there are several ingredients that go into solving the puzzle. It's a process that includes good analog components, matching Spice models, aggressive, but correct and well-documented process design rules, analog-pad cells with sufficient electrostatic discharge (ESD) and latch-up performance, a fast and compact logic design process with a versatile standard-cell set, good wire models, good ASIC vendor documentation, valuable and available IP blocks, and finally, a good ASIC design team willing to go the distance to assure customer success. The combination of all of these factors, if available, offers a powerful resolution to mixed-signal design challenges.

Working together on mixed-signal design

One example of a complex, mixed-signal design is the TC702, a mixed-signal, highly integrated controller for interactive televisions and Internet set-top box applications. At the heart of the Telecruz TC702 interactive platform is a complex 32-bit RISC ASIC. Along with this CPU core, the TC702 includes CPU peripherals, graphics processor, audio in and out, modem receive and transmit, video blanking interval (VBI) sync and data extractors, as well as other functions which require mixed-signal capability.

In order to develop the product, we had to define, architect, and design a chip with analog/mixed-signal capabilities, relying on a minimum of resources, and within a relatively short period. Therefore, a major decision revolved around which IP should be developed in-house and which should be outsourced.

Telecruz had the knowledge and resources in-house to develop all digital and analog technology. But in order to produce the TC702, we had to develop the final piece of the puzzleýthe CPU. The Telecruz engineering team decided that it would be necessary to find a design support team that could address the CPU features required in the chip. This turned out to be a major and bold decision. Though IP is widely discussed today, in actuality it's difficult to find IP that meets your needs exactly or IP that resides in the exact wafer-fabrication process requiredýespecially when the necessary IP includes analog sub-blocks. In addition, a CPU requires plenty of analog and semi-analog sub-blocks such as static RAMs and phase-locked loops (PLLs).

Criteria for ASIC design

One of the first major decisions the company faced was the selection of the CPU support team. Therefore, in the beginning, we looked throughout the industry to see who was available to offer that support, in addition to researching the appropriate software development tools, debug tools, CPU power metric, power consumption, die size, noise considerations, and so forth. Another key element in the decision-making process required selecting from ARM, MIPS, or other CPU architectures for the ASIC solution.

In addition, the process dimension also had to be sorted out. At the time, 0.35 ým was the standard, while 0.25 ým was still a new process generation and very expensive. Telecruz needed a low-cost process that would allow us to produce safe, reliable analog blocks like DACs and ADCs, PLLs and SRAMs. A major concern was that we had upwards of 15 analog blocks on the chip. To design analog blocks, we required an accurate, well-verified, and correlated Spice model, as well as an ASIC house that had well-documented layout-design rules, DRC flow, and LVS flow. We also needed a process that included what are normally referred to as analog componentsýresistors, capacitors, bipolar transistors, and their models (see Figure 3).

Additional considerations included standard-cell quality, back-end methodology, and the ASIC supplier's design team and commitment to project success. One of the specifications called for a well-modeled solution that would facilitate die-area utilization greater than 80 percent. We also reviewed the back-end design methodology of each potential supplier and the supplier's ability to integrate and verify blocks designed using different design methodologies, including standard cell, CPU with cache and PLL, as well as analog blocks. Even running full-chip LVS for such a complex design is important.

After considering various potential design partners, the company selected Toshiba America Electronic Components (TAEC) as the silicon partner whose capabilities most closely matched their own requirements. Toshiba offered the mixed-signal process capability, a MIPS CPU with MAC (multiply accumulate unit), a sufficiently large cache with JTAG, and the requisite 0.35-ým technology already verified. TAEC also had development boards to support product design, and links to software developers like Green Hills, GNU, and Wind River Systems.

Therefore, TAEC provided all requisite resources and documentation for the design of the TC702 RISC ASIC.

Merging IPs

Initially, one of the greatest challenges faced by the TAEC design team was the integration of a variety of IP. Before the design process had started, Telecruz had already developed the IP for the majority of the mixed-signal components: DAC, ADC, and PLLs. It was decided, therefore, that for the RISC ASIC, a strong design support team would be assigned from Telecruz to work with the Toshiba design center engineers in routing the circuit and completing the tape-out of the chip.

TAEC's 32-bit CPU core supporting MIPS architecture was selected for embedding into the interactive TV ASIC. Fortunately, it included peripherals to address direct- memory access and memory control. The CPU core arrived as a ýhard core,ý which meant that it came as a complete product (full layout done and timings verified for the CPU core). Design teams from both companies needed to be cognizant of the size and characteristics of this CPU core. It was necessary to leave the die size for the CPU blank while the design teams planned and implemented floor planning and routing for the TC702 RISC ASIC.

The teams also incorporated a significant amount of integrated IP, such as hardware, to support Telecruz' Cruzerware embedded software technology. Cruzerware provides support for the major Internet standards, communications protocols, and popular operating systems required for interactive applications. Tape-out for the rest of the chip was completed and TAEC engineers overlaid the CPU core to fit in the blank space left for it in the final die.

Mission Control, we have a problem

Right off the bat, a challenge arose when TAEC provided the design rules to Telecruz for its process technology. (Toshiba's TC220 0.35-ým technology technology was used to manufacture the TC702.) The analog voltages required that rings of the analog power-supply feed the mixed-signal design. Note that these cells of ADC, DAC, and PLLs were arranged by Telecruz; the place-and-route program wouldn't have been able to feed them properly. TAEC had to intervene in the automatic operation of the place-and-route functionýa problem that revealed inconsistencies in design methodologies between the two companies. These differences needed to be resolved to meet the customer needs.

Figure 2 - A plethora of requirements

Toshiba's TC260 (0.18µm) has different voltage requirements for the digital and analog circuitry.

As a result, TAEC developed new device-level models for Telecruz and handcrafted analog power-signals to satisfy the design-rule violations. The power supply was fed intermittently to all individual cells instead of just the cells tapping into the power ring. Layout was completed by Telecruz and their engineers were able to successfully write test vectors for the chip.

For the purposes of digital design, Telecruz used Verilog for RTL design and simulation, Synopsys' (Mountain View, CA) Design Compiler for synthesis, and Primetime for static timing analysis. The netlist synthesized from TAEC's cell library was passed on to TAEC for place and route. TAEC and Telecruz engineers worked together on placement, while TAEC did the routing.

For analog design, Telecruz supplied GDS-II files of one large and two small analog blocks to be dropped into the chip floorplan. The analog blocks passed Toshiba's DRC and LVS flows and were designed based on COT (customer-owned tooling) design rules provided by TAEC. One of the most elaborate activities was the pin-out and pad-ring design. Telecruz designed the pin-out based on TAEC's documented design rules and the pad ring was generated by TAEC. TAEC put all the blocks together based on a chip floorplan provided by Telecruz. TAEC performed final placement and routing and provided Telecruz timing files for back-annotated simulations of the digital blocks, including manufacturing test generators for different manufacturing testers. Telecruz used these tools to generate test vectors.

The design of the TC702 became a learning process for the two companies. Both engineering teams walked away with a better understanding of the specific requirements, challenges, and necessities required for analog/mixed-signal design. Throughout the process, Telecruz engineers provided constant feedback to the TAEC design center team with regards to their analog-cell behavior. Telecruz engineers, on the other hand, learned that placing their cell designs into the ASIC was never a trivial task. The place-and-route tool was often pushed beyond its limits. Designers determined that the answer wasn't to expect results from a push-button approach (where one feeds the parameters in a design system and an operator pushes a button to obtain the expected results).

TAEC had to develop new I/O cells to handle all of the signal regions of the chip. Engineers intervened in the automatic function of place and route to satisfy the powering of the analog cells placed in the chip. The 32-bit RISC CPU core was successfully merged with the mixed-signal IP and other digital logic from Telecruzýthe expectation for the chip being that it functioned well at 50 MHz. The end result yielded a fabricated part running at speeds of 70 MHz.

Going the extra mile

TAEC also handled the verification for the design and supplied the fault model for simulation. Using TAEC's design methodology, the TAEC design team was able to finalize the TC702 RISC ASIC with few engineering change orders (ECOs), saving at least six months of design time and helping Telecruz get their product to market months ahead of schedule. The RISC ASIC also offered performance that exceeded the original specifications due to TAEC's design efficiencies.

As outlined here, this cooperative methodology helps to cut down on design iterations by merging the synthesis process with logic-design planning, providing early timing predictability for complex ASIC designs. Logic-design planning includes floorplanning, timing-driven placement, global routing, timing estimation, area estimation, and tight links to synthesis and in-place optimization. By providing the Telecruz design team with physical information based on the same algorithms used in the final place-and-route phase, TAEC provided much faster timing closure for the deep-submicron design.

At all times during the project, there was a TAEC engineer assigned exclusively to the project, to serve as the interface between the two companies. During weekly meetings, all related activities were tracked and various issues were resolved, starting at the design phase and ending with packaging, testing, and manufacturing/qualification. During the place-and-route and test-vector generation phases, the engineers at both companies worked together closely to address the issues that arose.

Figure 3 - And the winner is...

As indicated by the functional block diagram, the TC702 system incorporated 1.5 analog blocks and Toshiba's TX39 in the design.

Single-chip functionality

Our mixed-signal design fits well with the description of a system-on-a-chip (SOC), for many reasons. It includes a CPU, digital and analog peripherals, memory controllers, and everything but the SDRAM and Flash EPROM required for the system. The RISC ASIC and its Bit BLT and vertical blank interval (VBI) co-processors pack together enough power to execute complex simultaneous tasksýlike graphics rendering, browsing, electronic program guide reception, and data communication.

The TC702 interactive platform from Telecruz provides television manufacturers with single-chip functionality to transform traditional television receivers into interactive-ready devices at minimal cost. Homes that previously didn't have access to the Internet in the U.S. and abroad have the ability to do e-commerce, e-mail, e-chat, and browse the Internet by using a minimum bill-of-materials set-top box and their television, or an advanced Internet-enabled TV set.

Execution

The initial phase of the project took about nine months to execute from design start to first silicon. The first silicon was suitable for samplingýanother indication of a successful joint effort by two expert teams. The fact that both teams were able to come together and create a RISC ASIC within this timeframe provided a significant benefit to Telecruz. As a direct result of the technology TAEC provided, the TC702 contains intricate IP and combines both analog and digital circuitry on a single chip. TAEC's SLI engineering team worked closely with the team at Telecruz throughout the design process, and utilized a hierarchical design methodology for modeling, place and route, and verification to integrate the analog and digital components required by the design.

Finally, when all engineers had successfully implemented their changes and the TC702 was complete, both companies walked away with a great sense of accomplishment, having completed the product months ahead of schedule, thus allowing for the introduction of the chip into various Internet-access capabilities at a critical time in the industry.

As the market for complex digital-consumer devices continues to grow, so will the need for analog/mixed-signal designs. Advanced technology companies like Telecruz will continue to work with ASIC vendors like TAEC for the development of critical mixed-signal, system-level solutions that integrate CPU cores. With gate counts continuing to increase and the amplified pressures on time-to-markets design schedules, ASIC vendors who are able to provide advanced design methodologies and CPU cores will be in demand.