Electrostatic Discharge (ESD) is an invisible destructive force that causes failure of electronic devices and reduces the reliability of electronic systems. ESD can cause damage and degrade electronic devices at any stage--during device manufacture, testing, handling, assembly, production, field operation, and handling of assembled boards in the field.

ESD occurs due to the accumulation of charges on a surface. This surface charge phenomenon results from the triboelectric effect--two materials rubbing against each other and generating a charge. There is a transfer of electrons from one surface to the other because one surface is negatively charged due to excess of electrons, and the other is positively charged due to the deficiency of electrons in equal measure.

Table 1
Positive End
1. Human Body	10. Cotton
2. Glass	11. Wood
3. Mica	12. Steel
4. Human hair	13. Rubber
5. Nylon	14. Polystyrene Foam
6. Wool	15. Polyester
7. Lead	16. Polythene
8. Aluminum	17. PVC
9. Paper	18. Teflon
	Negative end

When a charged surface comes in contact with another surface of a different potential, there is a transfer of electrons. A momentary current flow, sometimes a spark, takes place until the accumulated charge on the surface of the insulating material is neutralized. This transfer can occur in numerous environments: A person walking on a carpeted floor can generate high static voltages due to triboelectric charging, and voltages as high as 20 kV have been reported. Likewise, machines that use plastic parts can hold an electrostatic charge due to the plastic rubbing against other plastic parts. Additionally, high intensity electric and magnetic fields from equipment-a computer monitor operating on the AC mains--can induce static charge in components in the vicinity.

Table 2
No.	Device Type	Range of ESD Threshold (V)
1.	V-MOS	30-1200
2.	MOSFET, EPROM, GaAsFET	10-300
3.	JFET	150-7000
4.	OPAMP	190-2500
5.	Schottky Diodes	30-2500
6.	Film Resistors	300-3000
7.	SAW	150-500
8.	Schottky TTL	1000-2500
9.	CMOS	150-3000
10.	256K DRAM	200-3000
11.	Bipolar transistors	300-7000
12.	ECL	500-2000

ESD needn't always lead to failure of a component; it can cause a latent defect in the component, which can't be detected during routine testing. Such weakened components are more likely to fail in the field during system operation under harsh environmental conditions.

The capacity to release or absorb electrons varies for different materials and, based on this property, materials are classified according to the triboelectric series (see Table 1). The list covers the commonly encountered materials in every day production in an assembly environment.

Additionally, the device technology you select has a bearing on the ESD immunity of the product as a whole(see Table 2).

How does ESD affect semiconductor devices?

The increase of thin layers in semiconductor devices has made ESD a much deadlier adversary. Dielectric breakdown can easily rupture a device if a high voltage is impressed upon the thin film of an oxide in the device structures. A thin metallization trace can falter and open up like a fuse because of sudden large current flow and excessive I2R loss. Failure of p-n junctions can occur due to "current crowding"-when a large current flows through the respective junctions and causes high current densities. And ESD can cause Electrical Overstress (EOS) and melt the metallizations in a device (See Photographs 1 & 2).

Photograph 1 - Thermal overstress induced by EOS caused by ESD observed in a line transciever IC. Observe the damage seen inside the device.

Photograph 2 - ESD has burned a microscopic hole in the inner layer of a transciever chip by causing a high intensity electric field.

Photograph 3 - Charring of a data transciever due to ESD induced latch-up which has caused a cascading thermal overstress leading to burnup of the device.

Photograph 4 - Base-emitter short circuit observed in a bipolar junction transistor due to an ESD transient.

Latch-up failure

During one of my failure analysis studies, I found that a particular type of a CMOS RS-232 transceiver was failing often during the occurrence of lightning discharges. The chip would get burnt and the PCB would be damaged as well, making it unrepairable. To understand what caused the charring, the internal structure of the device was analyzed. I used IR microscopy (after back- polishing in some cases) and optical microscopy of the decapsulated devices to conduct my investigation.

Analysis revealed that ESD-induced latch-up had caused the device to fail (see Photo 3). The ESD transients were entering the device through the input and power supply pins. The latch-up problem occurred due to parasitic PNPN structures in the device. Such parasitic structures don't interfere with the normal device operation as long as the PNPN thyristor is in the OFF state. When latch-up occurs, the CMOS circuit behaves like a short circuit across the power supply.

Under normal conditions, the P-N junctions in the chip are all reverse-biased. Nevertheless, any voltage transient caused by ESD (See Photo 4), such as a voltage surge, or a noise pulse coupled into the device input or output, can trigger the parasitic Silicon-Controlled Rectifier (SCR) into conduction. Such an ESD voltage transient can be caused by lightning discharges, and these voltage transients could propagate into the device through the inputs or power supply pins. The triggering of the SCR structure causes a large current flow from VDD to VSS pins of the chip.

Additional latch-up processes

There are some other notable mechanisms for latch-up current generation within a chip. One such mechanism is the multiplication of current carriers by avalanche effect. Since the device under investigation used ý12V supplies and the gate-oxide thickness was considerably less, the avalanche effect was likely accentuated as compared with a single +5V operation device using the same technology, due to higher electric field conditions caused by higher voltage limits. A second source of latch-up current is the presence of parasitic field-effect transistors (FET). These FETs get paralleled with the lateral PNP transistors, and when the threshold for conduction is exceeded, latch-up current flows. The excessive total current flow due to the various latch-up currents causes over-heating of the device and thermal overstress, leading to charring of the device. The higher temperatures caused by the heat dissipation initially cause an increase in the carrier mobility and greater avalanche multiplication of carriers, aided by the higher electric field conditions (caused by the absolute difference of voltage between +12V and -12V). This process ultimately leads to the thermal overstress and the destruction of the device. The heat is also transferred from the hot device to the PCB, and therefore, the PCB beneath the device also gets charred. Hot spots, especially around the pins of the chip, indicate the large-scale heat transfer from the die to the leads.

Vendors need to latch-up to a standard

CMOS devices with small device geometries are particularly susceptible to an avalanche effect-type failure. Moreover, the susceptibility to latch-up is vendor related; the immunity to latch-up is dependent on the chip design and also on the manufacturing process used. Today, line transceivers with built-in transient suppressor diodes are available from a number of vendors. The transient suppressor within the chip clamps the spike voltage and prevents device damage, in the event of an ESD transient coming into the device.

ESD Models and Standards:

Based on the study of ESD effects and their causes observed over the years, models have been developed over the years to simulate ESD phenomena.

1. Human body model
2. Charged Device model
3. Field induced model
4. Machine model

Please see the sidebar for a more extensive description of each model.

Grounding and layout techniques play an important role in preventing ESD effects (see figures 3a & 3b). A larger current loop enclosed by a circuit creates larger flux linkages and will have a higher level of electrostatic and electromagnetic interference problems. Apply proper design guidelines in your circuit. Choose components that have a high ESD-tolerant voltage capability and use protection devices such as transient suppressor diodes and protection networks at critical points in the circuit.

ESD control starts from design

The first step to prevent ESD-induced failure is to start from the circuit design. Use devices of the right speed to achieve a desired function. The use of high-speed devices unnecessarily will increase problems, as a result of unwanted radiation and high-switching speeds. High-speed logic transitions will cause high-frequency fields that cause interference to other devices on the board. By anticipating the problems that could arise in the field, such as lightning and electromagnetic interference from nearby power lines in telecommunication devices, circuit design can be tailored to meet all possible contingencies.

As an example, we can cite the case of open-wire telephone lines, which can easily pickup ESD that's caused by lightning discharges. These interfering signals and induced-voltage transients can easily propagate into the cards and cause large-scale damage of electronic devices, unless suitable protection is installed in the system. Even if a device has built-in protective networks to prevent ESD damage, a higher level of protection using external components is often prudent.

Figure 3a - Bad layout - large loop area

Figure 3b - Better layout - reduced loop area

Diode suppressors offer protection

A well-known technique to suppress ESD energy is to use a transient-suppressor diode at critical points in the circuit. Such devices are essentially voltage-clamping tools with a fast response time. When an over-voltage transient caused by ESD or any other reason occurs, a transient suppressor clamps the voltage to a safe value according to its rating so that the device to which the transient suppressor is connected is protected. The power handling capability of the transient suppressor should be carefully chosen depending on the anticipated instantaneous power dissipation expected in the device.

As example of such an application, I cite the case of some types of RS-232 transceivers that require transient-suppressor diodes to be connected between input and output pins to ground. A simple technique to suppress ESD transients that can be used at the input stage of a circuit is to slip a ferrite bead on to the input lead and connect a low value capacitor from the input lead to ground (see Figure 4). The LC section at the input acts as a filter and diverts the energy in the ESD transient to ground.

In the absence of a low impedance ground, even protective devices such as transient-suppressor diodes will fail to protect any other devices that are connected to the common ground. In such a situation, the ground could be the culprit for failure. You need to have a clean ground for the proper functioning of many electronic circuits using a mixture of analog and digital circuits. While using transient suppressor diodes to protect any input or output, keep the transient suppressor very close to these terminals. Avoid long leads and PCB traces, since they have parasitic inductance and will cause voltage overshoots and ringing problems if an ESD transient gets into the circuit.

Figure 4 - Ferrite Bead used to prevent ESD in a digital circuit

PCB design guidelines

You can significantly reduce the incidence of ESD problems by having a well-planned and routed PCB. Electrostatic and magnetic lines of flux exist in every circuit-- due to the presence of different types of components and current flow through the circuit. If your board routing encloses large loop areas, the conducting paths will enclose more of the magnetic flux, which in turn will induce current in the loop (due to the loop acting as an antenna). This loop current will cause interfering fields that will affect components in the circuit. A method to reduce loop areas is to route supply and ground lines as close together as possible (see Figure 3a & 3b).

Use a low impedance ground in the board design so that any electrostatic discharge currents can easily flow to ground without finding other low-impedance paths through electronic devices. A ground area and preferably a ground plane will reduce ESD effects; unused areas in a PCB should be converted into ground plane. Signal lines should have ground lines running close to them. This will contribute to the reduction of loop areas and minimize ESD problems caused by large loops.

During placement of the board, ensure that sensitive electronic components are placed away from potential sources of ESD. Sensitive components should be kept away from transformers, coils, connectors, etc. Potential sources of ESD could accumulate charges or cause stray fields that can cause damage to the components.

Careless handling of PCBs in the field is responsible for a large percentage of field failures due to ESD. A good method is to provide a trace all round the PCB edge as a guard trace that should be connected to ground; this will discharge any static due to human contact. PCB routing should ensure the largest possible spacing between adjacent traces on the board in line with good CAD practices so that ESD pulses don't arc between adjacent traces and propagate. In most devices, protection devices should be used between the device pin and connector pin. Additionally, while designing logic circuits, try to avoid edge-triggered devices as much as possible. Such inputs are susceptible to cause malfunction of the system if an ESD transient finds its way into the circuit. It is preferable to use level -sensing logic with a validation strobe to improve ESD immunity of the circuit

If a sensitive device used in a circuit doesn't have built-in ESD protection, the circuit design should take care of this requirement. The required protection generally consists of connecting transient suppressor diodes at critical inputs and outputs to ground and series resistors at inputs to limit inrush current and usage of decoupling capacitors at the supply pins. If shielded cables are used, ensure that a full 360E contact with the shield is made to prevent antenna effects i.e., radiated fields.

Packaging ESD problems

ESD can be controlled to a large extent by using suitable materials such as static-dissipative tubes, bins, bags for packaging ESD-sensitive electronic components. In general, the materials used in any production environment can be categorized into the following types:insulating, antistatic, static dissipative, and conductive.

Insulating materials have a surface resistivity greater than 1014 W/square. They have a tendency to retain charge and grounding such materials will not be helpful, since current cannot flow through an insulator. Examples of such materials are plastics such as polyethylene, PVC, ceramics, rubber, etc. Plastics in combination with a conductive material or an antistatic material have application in protecting components against ESD.

Antistatic materials have surface resistivity in the range of 109-1014 W/square. Their lifetime is short and such materials can have limited re-use for storing assembled PCBs and electronic components. Due to the high surface resistivity, connecting such a material to ground will not be effective to bleed off any accumulated charge.

Static-dissipative materials have a surface resistivity in the range of 105-109 W/square. Due to their fairly low surface resistivity, charges on a component can be diverted to ground, if such a material is used to protect a component against static charge, and the static dissipative shield is grounded. Generally such materials are used to cover floors, table tops, assembly areas and for aprons.

The surface resistivity of conductive materials is less than 105 W/square. The charge accumulated on the surface of a conductive material can be discharged to ground. Plastics with a conductive material impregnated in them are used for packaging electronic components and PCBs in the electronic industry.

Helpful points on assembly and production

A number of materials-shielding bags and tubes for storing components and assembled boards-are available to protect components from ESD damage. ESD sensitive devices should be stored in antistatic tubes, bins or conductive foams specially designed for the purpose. The conductive surfaces in contact with the sensitive devices will bleed off the charges accumulated, avoid voltage differences between pins of the device, and prevent voltage build-up. A metallized polythene bag acts as a Faraday cage to protect devices stored in it from electric fields caused by charged bodies in the vicinity. For soldering ESD sensitive devices in PCBs, use a soldering iron whose tip has proper ground connection. Prevent the possibility of potential differences between pins of the device during handling. Cover unused communication connectors with static dissipative material when these are not in use to prevent charge build-up. Use antistatic material on worktables and floors in assembly areas to prevent generation of static electricity due to walking, etc. Assembly and test workers should wear antistatic wristbands with proper grounding and antistatic footwear.

Humidity helps

A humid atmosphere provides a means to discharge any atmospheric floating charges to ground and provide protection against static electricity build-up compared with dry air conditions. Air ionizers neutralize free charges and help in reducing ESD problems in assembly lines. Avoid tools with plastic handles since the handle can get charged due to triboelectric effect. Store assembled boards in antistatic bags. Ensure that antistatic precautions are observed while handling assembled PCBs in the field. Organize ESD awareness programs periodically so that all concerned personnel are informed about ESD damage and precautions to be observed.

Vigilance is the price of ESD-free design

Overcoming failures due to ESD requires total commitment to control techniques through the design, handling, assembly, testing, system integration, shipment, and operation stages of electronic. Memories, PLDs, FPGAs, ASICS, and SOCs are especially susceptible to ESD damage. You can minimize ESD damage to electronic devices by doing the following:

• Define the level of ESD protection required for various types of components used in your design. Some of them may be more susceptible than others. Identify ESD sensitive items. Take design precautions to provide adequate protection for such components i.e., achieve ESD immunity by design.
• Establish an ESD Control program in your organization. Identify potential problem areas, study failures, and develop methods to overcome them. Train workers at all levels and educate them on ESD damage and measures to prevent the same.
• Develop and implement a workable ESD check and correct program based on the needs of your organization. Remember that ESD control should be a continuous process and there are long-term benefits in terms of loss prevention and overall cost benefits.