From an R&D standpoint, combining a 104dB dynamic range, analog front-end on the same die with a 32-bit RISC processor is one of today's biggest mixed signal system-on-a-chip (SOC) challenges. Our team at Alcatel (Paris) met this problem by applying our own analog, digital and software development skills with a methodology that draws on commercially available EDA and laboratory verification tools.

By using our own design methodology we developed a mixed signal chip set-asynchronous digital subscriber line (ADSL) Dynamite (DMT) - that consisted of VHDL and Verilog HDL generated blocks, a microprocessor with embedded software, and analog circuitry. The DMT chip set has an interesting story of combining core system and chip design strengths.

The genesis of the DMT modem chip set

Alcatel telecommunication systems engineers designed the chips for the first ADSL modem. In 1993, they completed the design of a chip set consisting of two digital ASICs and one analog chip. At that time the ADSL physical protocol was implemented with an Intel 960 microcontroller as a separate chip.

This work formed the basis for the Alcatel Microelectronics business group to start with the designs completed by Alcatel system engineers and offer the ADSL modem chip set to the OEM market place. By 1992, Alcatel Microelectronics had decided to proceed with a product focus of fast access systems. At that time industry work on the ADSL set of standards had not begun. The company's concept was to provide a fully integrated "black box" solution with flexibility so that they and their customers could quickly adapt to new standards requirements and evolving market needs. The first DMT modem chip set release was in 1993. With Alcatel's own system knowledge and access to telecommunication operators as a respected supplier, they had tuned the chips at pilot sites.

By 1998 the fifth generation chip set, consisting of two ASSPs, was ready for the market. A data pump was added and the ARM7 TDMI processor core was replaced the Intel 960. The two digital chips were integrated into one chip for the 0.25 micron CMOS process, and the one analog chip remained in the 0.35 micron CMOS process (see Figure 1).

Figure 1 - ADSL DMTTM chipset - firfth generation

Example of a mixed mode SOC in Alcatel's CMOS process.

For the fifth generation, the front-end analog chip contained the physical interface to the line, the interface with the core engine, and digital representation. The digital chip contained the core engine, the DMT signal processor and the ATM framer. The modem is controlled with the embedded ARM7 microprocessor. Due to the flexible on-chip bus architecture, alternate digital back ends can easily be integrated onto the chip.

The modem is configurable with the chosen bus structure. Where real time performance is needed the implementation is in hardware. Additionally, the deductive DSP module can be programmed via the external controller. The FFT can be sized for variation in modulation by programming.

In order to reduce the area of the silicon, we set a high priority on the function of integration on the digital chip. For example, the custom DSP requires less area than would be required for a standard dedicated DSP. Power management design techniques were incorporated with portable applications in mind.

The design environment

The design environment available to the DMT chip set design team has evolved since 1993. Analog mixed signal simulation, high-level co-design and co-verification, embedded code development tools, and an IP reusable platform are examples of new capabilities now available in the design environment. As follows, Alcatel's goal is to design at the highest level of abstraction with the application of the latest tools and advanced methodologies.

Specification: For specification, either C or C++ is used to describe the hardware and software functions independent from the implementation. Designing at a high abstraction level allows for a smoother execution and for rapid consideration of system partitioning alternatives. By modeling the high-level specification - with concurrent refinement of alternatives - the most efficient and optimum partitioning of the architecture is possible. Depending upon system requirements such as functional, power consumption, cost, process technology capability, and IP block availability, the designer selects the preferred resources for the chip requirements. After extensive performance analysis, specified functions are implemented with a combination of software, a core processor, and high-level design language specified digital and analog functions. Some pre-designed functions are reused from the IP platform component library.

Co-Simulation: After specification and partitioning, co-simulation tools are utilized to verify consistency through the different abstraction levels. One unified test bench is used throughout the entire design flow. In addition, the use of a single simulation engine using C or C++ languages reduces the simulation time compared with typical methods using a combination of VHDL, C, and instruction set simulation (ISS).

During the DMT design phase, Alcatel made use of HW/SW co-design and verification tools from Coware (Santa Clara, CA). Luc Rottiers, Alcatel Microelectronics development engineer on the chip set project, credits the DMT design team's success with rapidly synchronizing the hardware and software to their use of Coware's N2C Design System.

Figure 2 - Co-design concurrent refinement

The existence of a simulation framework containing hardware and software allows for a continuous verification of the entire system, hence allowing for faster development and debugging of the software.

The Reusable Platform: We developed a flexible platform around the ST100 DSP processor and a family of 32 bit RISC cores from ARM (Cambridge). With this well-defined platform, new products can be developed quickly by concentrating the design effort on the selection and integration of peripheral intellectual property (IP) (see Figure 2).

The IP platform component includes several compilers for ROM and static RAM blocks, as well as a comprehensive set of high value added Application Specific

Functional Blocks (ASFB) for telecommunication and data processing applications. Telecommunication blocks include data pump engines for ADSL, ISDN, Ethernet, Bluetooth, and cable modem data pipelines. Value added analog blocks like broadband and/or high dynamic AD and DA converters, PLL, and pass-band filters are in the design system library.

Mixed-signal Design and Verification: For the design of analog blocks, we used a behavioral description of the analog circuits. High-level descriptions of the analog functions are created from the specification during the co-design phase. In-depth design and verification of the analog circuits is accomplished at the transistor level with Spice simulation. Top-level simulations are possible by running mixed mode simulation. The latest ADSL chip set was simulated with the Mentor Graphics' (Wilsonville, OR) Eldo analog simulator on a common backplane with a Verilog simulator. Any unique analog/digital interfaces are checked by this method.

Bit-wise comparisons are made between different levels of digital circuit representations. Analog models are verified in terms of functional results. For example, DC levels, stability analysis, AC plot, spectral results and noise plus offset evaluation. Back-end integration is controlled from the system. With the co-simulation capabilities, analog performances can be verified and significant software sequences can be simulated.

Figure 3 - The design flow

The design system presents a consistent view of timing and delay constraints, delay calculations, and library timing information.

Chip implementation environment

Register transfer level (RTL) design and entry is either in Verilog or VHDL. Throughout the design flow (see Figure 3) the design system presents a consistent view of timing and delay constraints, delay calculation, and library timing information. There is a tight coupling between the engines for logic synthesis and place/route. This enables the user of the system to quickly achieve timing convergence within the initial timing constraints. Verilog HDL, VHDL, and co-simulation tools can be used. For the back-end operation, we used floorplanning and place and route tools from Avanti (Fremont, CA). For physical layout, digital place and route tools operate from constraints imposed by sensitive analog blocks.

The system includes data for the tools based upon an accurate characterization of the libraries at a worst case scenario and with guaranteed accurate derating within a restricted range of voltage and temperature.

It's commonly understood that simulation of just 10 seconds of initialization could take days of simulation time. A hardware emulator is called upon for fast debug, particularly for the proving of the "handshaking" functions for communication between a central office and a user's modem. While simulation would likely take days, the emulator provides results within a few hours.

For laboratory prototyping the design environment allows for the mapping to FPGA test platforms for further debug.

Our team used the ARM development system for the controller design. They are available as IP blocks with functional descriptions in C, VHDL and Verilog co-simulation. Recently added capabilities to the ARM development tools for tracing the effects of microcode commands in logic with a logic analyzer have been useful to the designers.

First-pass proof

To anticipate future changes, we designed the DMT chip set with product enhancements in mind. Using the design architecture of the chip set and the design system environment the design team completed a USB version of the ADSL digital chip within one month from specification to tape out. The first-pass fabrication of the chip worked.

Bernard Goffart is technical marketing manager for Alcatel USA Microelectronics Group. Since 1993, Goffart has worked for Alcatel Microelectronics, where he serves as Technical Marketing Manager in the development and marketing of custom integrated circuit design for communications, automotive, and industrial applications.

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