A well-engineered power distribution network is critical to meeting the performance and reliability requirements of deep-submicron (DSM) system-on-a-chip (SOC) designs. As device densities and clock frequencies continue to increase, the switching currents carried by the power and ground networks increase as well, leading to an increase in power density. This increase coupled with the lower power supply voltages and thinner wires employed in DSM designs can adversely affect the robustness of the power grid. The power grid becomes more susceptible to large voltage drops at the devices due to high instantaneous currents and the resistance of the power supply lines, a phenomenon known as IR drop. The power supply lines also become more prone to the formation of voids and shorts to nearby wires due to electromigration caused by large sustained currents. IR (or voltage) drop not only affects power grid integrity, but also prolongs the timing closure loop. A five percent drop in the supply voltage of a gate can cause a fifteen percent increase in the gate delay. The impact of these DSM effects is that power grid verification has rapidly become a mandatory procedure for ensuring that a new design will work at its target speed, will meet reliability goals, and can be manufactured in volume.

Key challenge

A key challenge in power grid verification is that, until recently, most commercial power grid verification tools entered the design flow after layout was complete. At this late stage of the design cycle, one has the most detailed data on interconnect parasitics of the power supply lines and the current consumption of the devices. However, any power grid problems identified at this point can be extremely expensive to correct because of the amount of re-work required.

At Texas Instruments, Inc. (Dallas, TX), we have developed a new hierarchical power grid verification methodology for SOC designs that combines gate-level and transistor-level analyses. This multi-level, hierarchical verification methodology enables us to understand the flow and distribution of current through our SOC designs and catch potential power grid problems during the physical design cycle - as early as the floorplanning stage. We have validated this new methodology using one of our production SOC designs, the TMS320C6211 digital signal processor (DSP) chip.

Figure 1 - PGS methodology for SOC designs

Power grid characterizations are generated from GDSII layout for modeling current distribution.

As our first step in establishing our new power grid verification methodology, we defined our requirements. SOC designs incorporate multiple levels of logic and functionality on a single chip. Flat gate-level synthesized logic, hierarchical gate-level blocks, such as datapaths, and transistor-level embedded intellectual property (IP blocks), such as microprocessor cores or memories, as well as analog circuitry are all integrated onto a single die. Therefore, our SOC verification methodology had to be hierarchical and include both gate-level and transistor-level verification.

Gate-level analysis during the earlier stages of the design is useful in planning the top-level power grid and in specifying the power grid requirements for unassembled blocks.

However, gate-level analysis alone is not sufficiently accurate for power grid sign-off (PGS). So our methodology had to include power grid verification that modeled the internal power grid of cells or IP blocks down to the transistor-level to obtain accurate current distribution.

Figure 2 - VS SOC Flow

Analysis enables current flow through the DSP core and its impact on nearby logic to be seen.

Design reuse is central to SOC design, so our new methodology needed to support easy cell, block, and IP reuse. Once a cell or IP block was analyzed, we needed to be able to reuse those analysis results, rather than having to re-extract and re-analyze for each instance of the cell or IP block. This ability to reuse the analysis results would also significantly affect the turn-around time for full-chip power grid verification.

The power grid verification tool we selected to support our new methodology was Voltage Storm (VS) SOC from Simplex Solutions (Sunnyvale, CA), as it was a tool that could fulfill all the requirements of our desired multi-level and hierarchical approach.

Power grid sign-off methodology

The methodology we developed working with Simplex is shown in Figure 1. Initially, the library team characterizes and verifies all the leaf-level components in the design, including IP cores, memories, and standard cells. These power grid characterizations are generated at the transistor-level from GDSII layout to accurately model the current distribution. From these characterizations, library designers can create various power grid ýviewsý for use during verification: floorplan (or mockup) views, port (or blackbox) views, and detailed (or transistor-level) views.

The floorplan view is derived from the LEF description of the ports of a cell or block, and information such as the height of the cell and the width, spacing, and orientation of each metal layer used for power routing.

The port view is a blackbox view without transistors built from the LEF description of a cell library. It has current sources at ports on the periphery of the block.

It distributes current uniformly at the ports. This model can be useful for modeling standard cells at the floorplanning stage, but is inadequate for more complex IP blocks and for PGS.

The detailed power grid view for IP blocks and standard cells is built from the LEF description of the ports and the GDSII description of the layout. The components of the detailed power grid view include port geometries from the LEF, the internal power grid from the GDSII, and current sources at the transistor tap points derived from the GDSII layout. The detailed view contains transistor-level details that allow us to model accurately the current distribution and power consumption within complex IP blocks.

In the next stage of the design flow, the chip integration or physical design team analyzes the floorplan using a DEF description of the routing and the library of power grid views created by the library team. Module designers can use a similar approach to analyze their modules.

If the DEF is consistent with the final GDSII layout for tapeout, then for most ASIC flows, final PGS can be performed once all the cells and IP blocks have been placed along with the power routing. Having solid power grid integrity data at this stage of design enables designers to avoid excessive over-design of the power grid and maximizes the signal routing area.

Validating the methodology

If the design team has made significant changes to the final design after place and route, then the physical verification team, responsible for layout versus schematic verification and design rule checks, performs PGS at the transistor-level with a flat analysis on the final GDSII layout.

The design we used to validate this new methodology, the TMS320C6211, is a fixed-point advanced VLIW digital signal processor with a two-level cache-based memory architecture. The C6211 can produce two multiply-accumulates (MACs) per cycle for a total of 300 million MACs per second. With a performance of up to 1200 MIPS at a clock rate of 150 MHz, the C6211 is being used for JPEG image compression in network cameras, machine vision in defect detection scanners (for example, to scan semiconductor wafers for defects), raster image processing in printers and copiers for improved color quality and speed, multi-channel voice coders (such as g.723), and gateways for telecom applications.

The C6211 comprises six million transistors implemented in a five-layer metal process. There are approximately 116,000 routed nets and 229,000 placed objects represented in the DEF. The nominal power supply is 1.8 V.

Step 1: Power grid view generation

The first step in validating our new methodology was to create the power grid view library of the various components of the C6211. The C6211 DSP comprises a C62x advanced VLIW DSP core and contains 17 embedded SRAMs. Non-uniform current distribution in the DSP core and the embedded SRAMs necessitated the transistor-level modeling of the detailed power grid views created by VS SOC. We also created floorplan views of several of these elements, for use during the floorplanning process.

Step 2: Analysis during floorplanning

Early in the floorplanning stage, when the rest of the blocks were not yet created, we had access to the layout of the DSP core. The inputs to VS SOC for the full-chip analysis were the chip-level DEF of the global power routes, instance-based power consumption along with the detailed, transistor-level view of the DSP core and the floorplan views of the other blocks (See Figure 2). This analysis, performed after global power routing and placement but before signal routing, enabled us to see the current flow through the DSP core and its impact on the nearby logic. The analysis took only six minutes and 60MB of memory on a 400MHz SUN Ultrasparc-II workstation.

Figure 3 - Floorplanning stage results

Additional routing resources were available when the lowest voltage dropped.

It turned out that the power route was too conservative; we could tolerate more IR drop and still be within specification. We used the PGS Exploration feature in VS SOC to examine the effect of modifying the DEF for the power route. We used the scaling features to add wires and vias in areas of high IR drop and remove wires and vias in areas of low IR drop. The lowest voltage dropped from 1.774V to 1.770V, still within specification, and freed up valuable routing resources (See Figure 3).

Step 3: Power grid verification

After we performed global power routing, cell placement, and signal routing, we performed a full-chip hierarchical power grid IR drop verification. The inputs to VS SOC for this analysis were the chip-level DEF of signal and power routes, instance-based power consumption, and detailed views of the DSP core, SRAMs, and standard cells.

Figure 4 - Physical design stage results

Different views facilitate physical design.

For accurate power-consumption estimates for each block, we use a transistor-level simulation from Synopsys' (Mountain View, CA) Powermill. For pre-layout analysis, we create the SPICE deck required by Powermill from Synopsys' synthesized databases with wire-load model estimates of wire capacitance. For the post-layout analysis, we create the SPICE deck required by Powermill from a post-layout EDIF netlist with back-annotated parasitic capacitance extracted with Simplex' Fire & Ice QX.

Figure 5 - Comparison between flat and hierarchal analysis

The calculated voltages were within 0.1 percent.

To estimate the maximum power dissipation of each block, we use an actual application that will be run on the chip, such as a GSM vocoder, or we create a test case that ensures maximum switching of all busses, functional units and caches within the design block. Using an actual application ensures correlation across functional blocks in the chip. We run a functional simulation of the maximum-power test case on the block to capture the inputs and outputs (I/O) of the block during simulation. We use scripts to translate the I/O vectors of the block from the functional VHDL simulator (Synopsys' VSS) into Powermill vector format. We perform a Powermill simulation using the SPICE deck for the block and vectors derived from the maximum-power test case to get an estimate of the power consumption of the block. We use this estimate as the instance-based power consumption input to VS SOC.

Figure 6 - Impact of IR drop on timing verification.

IR drop had a significant impact on timing.

The full-chip hierarchical analysis with VS SOC on the final DEF took 22 minutes and 550MB of memory on a 400MHz SUN Ultrasparc-II workstation.

In addition to IR drop analysis, it produces several other power grid visualizations, including resistor current, tap current, and current density plots. The plots shown in Figure 4 were very helpful in visualizing the behavior of the power grid. For example, the distribution of tap currents shows very low currents in the memories, and high currents in the DSP core, which verified that the current distribution was as we expected.

Accuracy validation

The DEF-based analysis with VS SOC was very fast - 22 CPU minutes compared with 17.5 CPU hours for our existing post-layout transistor-level power grid extraction and analysis. But we also wanted to be sure about the accuracy of the analysis. To validate the accuracy of the hierarchical analysis, we performed a flat, transistor-level analysis of the power grid using our existing power grid verification methodology on the final GDSII layout.

The minimum operating voltage calculated from the flat, GDSII-based, transistor-level analysis was 1.7477V, an IR drop of 0.0523V. The minimum operating voltage calculated from the hierarchical analysis was 1.7472V, an IR drop of 0.0528V - almost identical to the transistor-level analysis result - within 0.1 percent (see Figure 5).

Simplex attributes this accuracy to a proprietary technology they call Accura static analysis, which analyzes clock domains, recognizes memories and gates, and propagates activity from primary inputs.

Impact on timing

Non-uniform power distribution affects chip performance and must be comprehended in DSM SOC timing verification. The effect of IR drop on timing has been ignored in discussions of the timing closure loop because of the difficulty in obtaining this data, and the long turn-around time of flat transistor-level analysis. We conducted an experiment to understand the effect of IR drop on timing by feeding the instance-based IR drop results from VS SOC hierarchical analysis into our delay calculator, Synopsys' Primetime.

We used a manual approach to feed instance-based IR drop into Primetime. We created multiple Synopsys cell libraries for varying levels of IR drop (2 percent, 5 percent, 10 percent). Then, we selected the library elements for the Primetime analysis based on the IR drop data from VS SOC.

The results of this experiment are shown in Figure 6. Though rather crude, the experiment revealed the significant impact of IR drop on timing. The IR drop affected worst case paths and paths with negative slack as can be seen in the figure. The value of an IR-drop-aware timing verification flow is clear.

Conclusions

Power grid verification is an essential part of any DSM SOC design methodology. Using VS SOC, we were able to develop a new hierarchical methodology for power grid verification that includes gate-level and transistor-level analyses. We are now able to visualize the behavior of current in our designs and verify the integrity of our power grid designs early in the physical design cycle. Early analysis enables us to make power grid changes when they are easiest and least costly to implement.

It also helps us avoid needless and ubiquitous over-design of the power grid. Finally, we were able to demonstrate the value of including IR drop data in our timing verification flow.

Robin C. Sarma is responsible for deep-submicron EDA methodology for DSP designs at Texas Instruments, Inc. He interfaces between the design, manufacturing, and silicon technology development functions to ensure that TI's advanced DSPs can ramp to volume with target yield, performance, and reliability.

Arjun Rajagopal is an IC designer in the Dallas DSP Department at Texas Instruments, Inc. His responsibilities include power grid design and verification. His interests encompass interconnect modeling, clock tree design, and analysis.

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