The plenary session at the IEEE ASIC/SOC (Washington D.C., September 2000) conference featured a presentation from Wolfgang Roething, EDA manager at NEC Electronics, entitled "Design for Signal Integrity on SOC." The talk illustrated the many ways that signal integrity issues can affect the performance of an integrated circuit. At the request of ISD Magazine, Tets Maniwa attended the session and summarized Roething's comments.

Signal integrity problems result from the interaction of coupled signals. The consequences of inattention to the issues are cross-talk (one signal causes problems with another), reduced reliability and manufacturability, and lowered system-level performance. In custom methodologies, performance is eked out circuit by circuit; signal integrity issues are addressed by designing individual circuits for optimal performance.

In ASIC (application-specific IC) designs, much of the performance is sacrificed to standard cells, fast-development times, and wide margins and guard bands. The high-end ASICs need to bridge the gap and deliver high performance along with short development times.

Developments in process technologies are increasing the chances for cross talk. The number of metal layers continues to climb-from 4 or 5 in the 0.35-micron process node to over 7 in the 0.13-micron process. As the number of wire layers increases, the adjacent channel capacitance increases as well. Additionally, the number of gates in today's complex designs is necessitating more and longer interconnects. This longer set of wires increases the resistance to increase. The narrower metals also contribute to increased resistance, since the cross section area is going down. The transition to copper interconnect isn't solving, but only delaying resistance problems.

Clearly, these adjacent wire affects now dominate design decisions and are requiring different, more accurate models. The effect of one signal on another is a function of the relative phase of the signals. For in-phase signals, the victim net can be speeded up by 30 percent for small drivers and receivers on a 0.5-mm line. For a 1-mm line, the victim net can show a 40 percent increase in speed. For opposing signals, the victim net slows by as much as 70 percent for small drivers and receivers on a 0.5-mm line, and over 100 percent on a 1-mm line.

One of the possible solutions to cross talk is to increase the spacing of the metals. Doubling the wire pitch can reduce cross talk from as much as 70 percent to as little as 20 percent on the 0.5-mm line. Long line interference (1-mm line) can go from 100 percent down to 40 percent. However, cross talk still exists and doubling the metal pitch to reduce cross talk actually increases area and routing problems.

Add a shield

Another way to address the issue is to add shielding. By putting a ground or power line on both sides of a signal line, cross talk is greatly reduced. Putting shields into a system also requires the packaged part be well bypassed and that power and ground sources be relatively quiet. In fact, this solution is even worse than the double metal pitch solution from an area perspective, because the spacing of signal lines is 4 times the minimum spacing and, therefore, the interleaving of the ground lines makes routing an order of magnitude more complex.

Shielding is appropriate, however, for some lines-for instance, clock lines-which have the highest speeds and the largest drivers and buffers through the net. The use of phase-locked loops (PLLs) can help to compensate for extra delays in drivers and buffers. A layout that maintains an isolated environment for the clocks will minimize the chances for the clock lines to interfere with the data signals.

In this approach, the designer uses extraction and analysis tools to detect areas susceptible to signal integrity problems, and then has several to implement a fix. If the problem signal line is relatively isolated, re-routing the line can offer a solution. The simpler strategy is to change driver sizes and add buffers on the victim nets.

Drivers are often selected during the synthesis process using approximations of wire loads. In general, synthesis picks the next highest driver to overcompensate for the expected loads. However, the actual loading isn't available until the physical design is complete and may vary from predicted loads across a range from -70 percent to +200 percent. In the worst scenario, an oversized driver is on a short line next to a lightly loaded long line.

One solution to the driver problem is to break the long line with a buffer. This reduces line length and decreases coupling capacitance while also reducing the loading on the input side of the buffer to a single load. The technique preserves the floor plan and optimizations done during the routing process with only small perturbations in the layout for the buffers.

To deal with noise and delay, the process adds steps to the static timing analysis portion of the design flow. The intent is to integrate the flow for addressing cross talk and timing. First the tools extract the layout parasitics. Next, the delays are calculated without any cross-talk affect from the extracted loading models. These extracted delays are then back annotated into the design and the static timing analysis tool used to determine the uncorrected timing. After getting a first approximation of the timing windows, the designer inserts the cross-talk delays and checks for timing that may fall outside of the allocated window. The complete process requires three passes through the static timing analysis phase.

Reliability and manufacturability

The trend in the industry today is to continue to increase gate counts-and performance-by shrinking feature size. Additionally, the outcome of obedience to Moore's Law is to increase clocks and gate counts to achieve a doubling of performance every 18 months. To maintain safe operating limits in these designs, the power supplies must decrease with every process technology shrink. Meanwhile, the power per gate is also decreasing. The changes in power consumption due to reductions in supply voltages and power per gate isn't, however, keeping up with the increased gate counts and clock frequencies.

The high performance circuits-processors, for instance-are projected to consume 300 watts at 1.8 volts in the next generation of process technologies. The average ASIC will have 34 million gates and will clock at over 450 MHz. The supply current for the next generation ASIC will be much higher than anything running today. Dramatically, the 0.18-micron ASIC will consume over 6 times the power and over 10 time the current densities of its 0.35-micron counterpart.

One troubling result of the increased power and current is electro-migration. The high power nets with unidirectional flow will see metal migration due to the flow of the current-especially where the current goes around corners or into constricted spaces. A similar effect occurs in the lines with bi-directional current flows due to the self-heating associated with points of higher resistivity.

The reductions in feature size also require a tracking decrease in the gate oxides. The high fields in the switching circuits can trap electrons in the gate oxide. The damage to the oxide and consequent shift in thresholds is a cumulative process that is related to the switching frequency-it has a slew-rate dependency.

If the switching frequencies are maintained below a safe limit, the part can be predicted to have a normal operating lifetime. However, the challenge comes is developing a methodology that controls hot-electron effects for frequencies or slew rates above the safe limits. Users need to fully characterize these effects. First, they must simulate transient conditions on the internal standard-cell circuits. Then, they must compare the simulation results with current density limits and with the test results from silicon structures. Finally, they need to create models that accurately reflect the actual devices and processes.

Circuit analysis can follow a number of alternative methods, all of which require the calculation of the actual switching frequencies. One way to solve the problem is to simulate all circuits for an exact response based on the characterization model. The other way is to develop probabilistic models that closely compare to the actual behaviors in the silicon structures.

To repair the problems associated with metal migration and hot electron injection, the first approach is to insert buffers into the long lines-the ones most likely to have higher currents and faster switching signals. This repair, once again, reduces the loading capacitance on the lines and lowers the slew rate if the buffer is a barely undersized driver. An alternative repair method changes the driver and receiver cells, a significantly more intrusive process in today's technologies.

Antenna effects and noise

The plasma etch process on the metal layers forces charge to collect on the gates of the IC. The ratio of smaller gate area and increased interconnect lengths results in a capacitive voltage divider, which in turn leads to further damage-again, cumulative. The basic method for minimizing these antenna effects are to put limits on the ratio of metal area to perimeter length, as well as gate area to perimeter length. These rules will reduce the charge collection and transfer process.

An alternative strategy is to use a route tool that relies on antenna correct routing rules. This prevents or minimizes the antenna currents, although at the expense of greater area. Another possibility is to connect the long antenna to diffusions and to let the diffused resistors divert the charge to some other area (for instance, the substrate). Finally, the insertion of buffers reduces the lengths and inserts diffused resistors-the P and N output transistor channels-as resistive paths to the power supply and ground.

The increase in power consumption and supply current causes other problems as well. The high currents precipitate voltage drops on the supply lines, thus reducing the voltage available to the gates due to the IR drop of those currents through the non-zero resistance of the power grid lines. The increase in power to the rails is greater than the reduction in resistance that results from either wider lines or migrating from aluminum to copper.

Possible decreases in resistance in the power grid are limited by area and routing congestion. Performing extraction and analysis at the physical verification stage requires a complex, full-chip simulation including transients, and inductive and capacitive effects.

Even worse, little or no repair is possible at the finished layout level. The best way to address the power issue is to plan and implement strategies at the very earliest stages of the design, when the process is still in the RTL stages. A highly accurate power analysis of the RTL has to link to the logical and physical implementations in order to insure quality in the resulting design.

Prescriptions for next generation tools

The total design process is going to have to evolve to a set of multi-variant effects and evaluations if the problems outlined here are to be addressed. The various tools will need to pass intelligent data-for instance, the emerging advanced library format (ALF) standards which support mathematical models that pass on multiple attributes without requiring changes in calculations and data formats. The new highly complex and demanding designs will need early planing to address issues early in the design flow where the changes will be most effective. The links between the design, verification,

layout, and final physical verification all need to consistently exchange data, but without changing the data or requiring additional calculations.

By moving to ALF, users are able to generate test vectors that check power and electro-migration, while at the same time they test functionality. The test vectors can use a probabilistic reference to the extracted silicon data to maintain the necessary accuracy. By looking carefully at the whole design in this way, early in the design cycle, at the RT level, the designer can solutions that minimize cross-talk through meticulous planning, floor planning, and power analysis. The development of asynchronous clock drivers for some sections of the design will reduce power surges which result from the whole chip switching simultaneously, while reducing noise and power grid IR drop at the same time.

Unfortunately, the existing commercial tools are of marginal value for the next generation of designs. Although most ASIC vendors have internal tool development groups, most of their current work involves integrating the separate tolls and creating shells for the tools to allow them to run under automated scripts. In the near future, we will see the number of internally developed tools increase as the design issues overwhelm the existing, commercially available tools.

However, the difficulty with in-house tools is that they require markedly more support training than vendor-supplied tools. Internal tool developers aren't in the business of making tools that are easy to use and easy to maintain. They are just scrambling to provide solutions for the immediate and critical problems of the users-the design teams.

Tets Maniwa is Community Leader for EDA on CMP's website for digital designers, EEdesign.com. Formerly, he was Editor of ISD Magazine.

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