The push towards SOC complexities and the rush to shorter and shorter development cycle times is forcing a major shift in the way new designs are being developed. Identified solutions to this problem include efficient design reuse across organizational and company boundaries as well as an improved and modified SOC development environment that can take full advantage of that reusable IP as the move towards system-level design progresses.

Semiconductor providers have started internal initiatives to develop and deploy these new SOC development and design reuse methodologies across their organizations. Some smaller companies have successfully transitioned already to a reuse-based mentality, while larger companies still struggle with their dispersed organizations and cultural as well as methodological diversities.

Back in the era of mainframe computing, design methodologies were centralized and standardized across a company. However, the advent of Unix workstations and the decentralization of design efforts brought with it the decentralization and thus the diversity of design methodology development. To address SOC-related design methodology issues and to establish efficient design reuse across a company, we at Motorola's Semiconductor Product Sector (SPS) have now returned once again to a more centralized approach.

Our customers' demand for system-on-a-chip designs within shorter and shorter development cycles has forced us to focus on required improvements to the SOC development process changes that span the spectrum from system-level design to mask fabrication. We have established a central EDA organization to implement the required changes in methodology development and deployment. Because of the large size of our company and the diversity in its talents and target market requirements, it's critically important that all involved parties achieve close collaboration to enable development and, even more importantly, deployment of an improved SOC development ecosystem. Top-level management support, very critical for the success of this initiative, was established early on. We're using a variety of methods to include design management in the decision-making process as well as to keep the design community regularly informed about progress in this area. Major steps towards a company-wide reuse infrastructure have included a central web-based IP repository and a comprehensive set of reuse standards.

Cycle analysis

Several years ago, an earlier attempt to establish a common design environment across the sector was only marginally successful; the cultural aspects of such required changes within the design community hadn't yet been properly addressed.

To avoid these pitfalls and to better understand the specific customer issues in this next undertaking, we performed a large-scale assessment across SPS its geographically dispersed locations and various market business groups. Over a period of three months, assessment teams visited many of the design groups and interviewed a large portion of the people involved in design projects. These people included Motorola SPS designers and senior managers as well as selected customers and industry analysts.

The objective of the assessment was to understand the diversity in existing design methodologies and to highlight current practices that support or detract from SOC and reuse efforts. The assessment was also used to determine industry trends and requirements for future enhancements to these methods and practices, as well as to identify roadblocks preventing their development and deployment. Finally, based on the findings, we established a plan to develop and deploy improved methodologies to foster more rapid development of system-on-a-chip solutions for Motorola SPS customers.

Three challenges

Throughout the assessments, the design community gave consistent messages describing three types of challenges: cultural, technical, and transitional.

Cultural challenges present formal and informal impediments to SOC design and IP reuse. For example, no visible economic incentives at the organizational or individual level appear to promote reuse principles in IP creation and integration. IP creators focus on optimizing at the component (core) level, thus valuing performance and innovation, which results in an emphasis at odds with the product groups groups that emphasize time-to-market and reusability at the systems level.

Previous centralized CAD efforts with their legacy of credibility issues such as poor communication and accountability could hinder this new effort. What most undermines credibility, however, is the perceived lack of management commitment to the longevity of such an initiative.

The technical challenges address the areas of reuse standards, IP management, and design methodologies. The lack of company-wide reuse standards limits the efficiency of current reuse practices beyond design group boundaries. Reused IP typically suffers from an incomplete set of deliverables and poor documentation as well as incompatible formats, design styles, bus interfaces, and verification environments.

The lack of an IP infrastructure also inhibits design reuse. There is currently no mechanism to identify available IP or to consolidate IP needs across the company. Distributed groups lack the time and skill to negotiate the complex legal agreements demanded by the procurement of IP. Support for IP is also inadequate.

The lack of standardized design methodologies, design tools, and reference flows across SPS impairs collaboration through the sharing of design data or resources. Standardization often implies inflexibility a problem for groups that must employ cutting-edge tools to develop high-performance designs. Superior customer support, indicated by responsiveness and reliability, is key to making a standardized tool set into a competitive asset.

As part of the assessments, we analyzed designs and associated design processes to establish a figure for the efficiency of the development process. Using a third-party metric allowed us to quantify the design flow efficiencies and to benchmark them against industry data points. The results emphasize the great diversity in design flows across the company and provide the baseline needed for correlation with future measurements in order to monitor progress.

Highly recommended

SPS clearly must improve the amount and the efficiency of design reuse to produce SOC designs in acceptable time-to-market and at reasonable expense. In order to reuse IP, SPS must standardize on IP deliverables, cell libraries, and design tools. A central repository must be made available to efficiently share the IP across the company. This effort will not only enable efficient IP reuse, but will also bring economies of scale to the support of tools and libraries, and therefore reduce duplication of effort.

For instance, to better support IP reuse and to include system level and analog-mixed signal design flows, we find that we have to establish an improved SOC development ecosystem based on common methodologies and flows utilizing current best practices. Everyone involved in the product development process has a part to play in improving SOC design capabilities and IP reuse across the sector.

To move forward, SPS senior management must deliver a public mandate to modify the way in which products are developed within the sector and assign a central organization to oversee such a change. The SPS leadership team must also align the goals of product development groups and IP creators, and thus provide incentives for them to embrace design reuse when it makes economic sense.

This initiative must leverage existing industry or SPS standards in evolving IP reuse and design system products. In addition, the central organization must interact closely with the design community, through collaboration, needs assessments, design services, training, and communications.

IP creators need to ensure that they thoroughly understand the system-level goals of the target product development group as well as those of the end customer. IP creators must also participate in the development and adoption of reuse standards for IP deliverables, methodologies, and tools. IP creators must migrate to synthesizable cores to allow for rapid retargetability into new technologies, and to extend the possible lifetime of the IP.

To enable a true system-on-a-chip development, we emphasized system-level design methodologies as well as the integration of software development in the SOC development process.

Product development groups must strive to obtain system-level design expertise, either through training, acquisition, or close partnership with the end customer. Product development groups must also participate in the development and adoption of reuse standards for IP deliverables, methodologies, and tools and they need to communicate future IP needs and priorities to the central organization.

On the other side

We presented the results of the assessment, the compiled recommendations, and our plans to SPS management.

To enable efficient IP reuse across organizational boundaries, we needed a dedicated reuse infrastructure that would center on a central IP repository for the cataloging and sharing of IP and would stem from reuse standards specifying the exact requirements to IP creators. The reuse standards also set the expectations with the IP integrators in terms of IP deliverables, their content, and the associated quality metrics. We also required a certification process to allow for compliance checking of IP against the standards and to grade IP before it goes into the repository. Automation would help with the development of standards-compliant IP deliverables, as well as support certification. A service and support organization would help IP creators to minimize the impact of the additional effort associated with design-for-reuse (DFR) and provide hands-on training for the automation. Finally, an IP roadmap detailing the IP needs of the product group for the next 12 to 18 months would allow for the timely acquisition or development of efficiently reusable IP (see the figure).

Figure 1 - A reusable design flow

The dedicated reuse infrastructure unites protocols, standards, and library information with the efforts of designers across the sector.

To enable true system-on-a-chip development, we emphasized system-level design methodologies as well as the integration of software development into the SOC development process. Reductions in the development cycle time demanded the maximum possible automation of the chip implementation flow from RTL to GDSII. In turn, automation required a standardized flow. Therefore, we had to establish a common and standardized SOC development methodology, including system-level and software development based on existing best practices. Strategic point tool development was to be included where necessary. Close ties to analog and mixed-signal design flow development would ensure correct interfaces between the digital and the analog portions of an SOC design.

Since they form the basis for any SOC development, libraries and memories are critical components that had to be tightly integrated into the SOC development ecosystem.

To address the important cultural aspects of such a company-wide undertaking, we initiated an SOC awareness campaign to educate the design community.

Sufficient training, support, and services associated with all aspects of this improved methodology had to be provided. An application engineering function would support SOC developers with the integration of IP, specifically core IP.

Since the assessments showed that the cultural challenges are critical roadblocks for adoption of DFR practices and an improved SOC development methodology, we also proposed establishing a marketing group that could promote and raise awareness of new methods while also serving as the customer interface. In order to interface these various pieces of methodologies together seamlessly to form the complete SOC development ecosystem, we strongly recommended combining the various development activities into one central EDA organization. Strong upper management support had to be established and a clear statement made for SPS to move towards common SOC development and reuse methodologies.

In early 1998, we formed the SOC design technology (SOCDT) organization by restructuring a previously existing central EDA organization and merging it with several other related groups.

Do you know the way to SOC?

SOCDT has made substantial progress over the past two years. A very important aspect of the progress is the close collaboration with the product development groups along with support from sector management. To involve these groups more closely in the strategic definition and decision making process, we formed an advisory board made up of representative high-level design managers from the various market business groups and core technology centers as well as a few selected customers from within the company. This group meets regularly to discuss and review the SOCDT strategic projects and to check their alignment with the sector strategy.

On the technical level, we've defined pilot projects to drive the methodology development. People from the product groups and the central EDA organization are working together to establish the improved and sometimes new methodologies incorporating the existing best practices.

This collaboration has so far resulted in the development of the second generation of comprehensive reuse standards and associated automation for the development and certification of reusable IP. To catalog and share this IP, we developed a sophisticated central web-based IP repository.

In hoping to address the increased design cycle time that the additional DFR effort may precipitate, we're establishing an IP roadmap and a service team. Because the roadmap identifies the IP needs for the group over the next 12 to 18 months, we can acquire or develop the IP ahead of time and then make it available when it's needed. The service team will collaborate with the project group to work specifically on design blocks that either the next-generation design or another design team has identified for reuse. These additional resources bring in the expertise and automation needed to reduce the amount of additional effort required, thereby helping to minimize the impact on the design development schedule. Finally, we've released a first version of the SOC development ecosystem, currently being used by one group to develop an automotive platform design.

To address the important cultural aspects of such a company-wide undertaking, we initiated an SOC awareness campaign to educate the design community about the needs for the change in design mentality as well as to communicate the goals and benefits of this initiative for SPS and ultimately for its customers. We're calling our campaign Route 66.

As mentioned, the assessment results revealed negligible economic incentives promoting reuse principles. The community had highlighted the issue as a critical roadblock to the adoption of a reuse infrastructure. Therefore, we formed a cross-functional team to discuss the requirements necessary for establishing such incentives on an organizational as well as individual level to encourage and reward a reuse mentality.

Several metrics will help us to measure progress and to determine improvements in SOC development cycle times.

To ensure continuous communication between the central EDA organization and the design community, we've assembled a marketing team to ensure regular communications. The team, also responsible for education and training, is developing a detailed SOC curriculum to address all aspects of the SOC design flow.

Several metrics will help us to measure progress and to determine the improvements in SOC development cycle times. The results will help us to identify best practices to leverage in future developments, to provide benchmark data between SPS designs and industry data points, and to report progress to upper-level management on a regular basis.

The first version of an SOC development system one that includes system-level and mixed-signal design flow capabilities has served in the development of a platform design for the automotive market. However, substantial effort still lies ahead. The next steps will focus on refining and enhancing the currently developed methods, and making them more usable by an increasing number of design groups across the company.

Thomas Harms is the technical marketing manager of the SOCDT of Motorola Corp. in Austin. He has over 10 years of experience in design methodology development.