In the mid '90s Philips Semiconductors formed a team to develop an analog TV solution with a much improved price point. The initial plan was to investigate how we could deliver these functions through a system on a chip (SOC). However, it soon became clear that this approach would have potentially taken longer to achieve than was desirable in an extremely competitive market. Instead, we pursued an integrated design that we could implement as two separate chips using optimal process technologies, mounted in a single package.

The road to digital

For years, the functional core of the TV system has remained relentlessly analog. More recent developments of on-screen displays, teletext, and other graphic elements have introduced digital functions. The higher-end sets have incorporated these digital capabilities, providing improved picture quality through color manipulation, while doubling the scan frequency.

Digital broadcasting will, over time, eliminate analog circuitry from much of the set (guns for the tube will still require digital-to-analog converters, but sets using plasma displays will be almost 100 percent digital). However, these virtually all-digital sets will appear only at the top end of the market. For at least the next ten years, analog sets will continue to dominate the mid-level and lower-end markets, and will use set top boxes to receive digital broadcasts.

In the early 1990s we released a dual PAL/NTSC picture processor combining IF functions and picture synchronization. The chip used a proprietary BiMOS process developed for video applications and optimized for bipolar circuits with additional CMOS features for digital use. Unlike processes optimized for CMOS with bipolar features, our BiMOS uses CMOS digital libraries under heavy time constraints. The current generation of one-chip TV is fabricated in BiMOS2, and includes an I2C bus interface, SECAM decoding, and a PAL delay line. The recently developed BiMOS3 process technology provides even smaller features and higher frequency capability.

In addition to TV signal processors, we have developed teletext products that handle closed captioning and other on-screen display (OSD) functions. These have been fabricated in a proprietary CMOS process and, in the later generations, have also begun to include an embedded 80C51 micro-controller.

Making the tradeoffs

Customers are constantly looking to reduce manufacturing costs, a requirement considered critical to future product planning efforts. While the new BiMOS3 offered increased density, it provided no board-level savings. Fortunately, combining the signal processor with the digital technology of the microcontroller and screen graphics provided the potential savings in device count, and thus board real estate.

The definition process for the UOC included evaluating a continuing series of tradeoffs, balancing what was theoretically possible with existing technology and time-to-market risks. The first of these tradeoffs was the fundamental decision to continue to segment the design into two separate die that were then mounted onto a single lead frame. The lead frame would provide communications between the die, eliminating the need to integrate both die onto a single chip. However, the potential savings of a single-chip device were relatively small compared to the technology risk and time required to recreate the design for a different technology.

The resultant package required only 64 pins, a considerable savings over the two 52- and 56-pin packages previously used. A significant pin-count savings came out of the fact that the I2C bus could communicate between the two chips across the lead frame, rather than having to transfer information between two packages. Eliminating the need for drive transistors, pull-up resistors, buffering transistors, and flash-protection resistors and capacitors also saved over 122 external components.

Figure 1 - The UOC system

The block outlines the entire system, with the BiMOS circuitry marked in red and the CMOS in blue.

As the design process continued, we also decided not to move circuit elements from one die to another. For example, we could have implemented the RGB drivers that formed part of the digital processor very efficiently in the BiMOS used for the signal processor. However, they were already working well in the signal processor, and moving them would have required both a new design and a marked increase in the number of links between the two die.

We did, however, make some changes, such as using a single crystal rather than five. These crystals previously sent four signals to the signal processor, providing timing for color references and synchronization; the digital circuitry used only one signal. In the present design, a single crystal provides a base reference that the system then uses to derive color references in the picture processor. This revision reduces both the overall component count and the package pin count and acts, as well, as a standard reference across the interface between the two .

Once we had made these decisions, the formal definition of the interface was a relatively simple process. It contained only 17 connections (see the table). Most of these were, like the I2C bus, self-defining but formal definitions were produced for each of them. Upon formal definition completion, we proceeded with the two designs in parallel (see Figure 1).

Analogous design

Since we planned to implement the analog circuitry in a new version of the BiMOS process technology, we had to create a new layout for all the circuits within the chip. We used the conventional approach of decomposing the overall device into functional blocks, assigning each block and its functional specification to a designer. In some cases it was possible just to evolve from an existing design to one using the new technologies. For others, particularly those concerned with the shared clock (instead of individual clocks); we needed a completely new design.

Each designer had to prepare a complete circuit design-by hand-before the layout team prepared the layout-by hand-using Cadence Virtuoso tools. We then hand-checked the completed layout for design-rule conformity, layout versus schematic (LVS), and matching.

To provide simulation, we developed a suite of tools, using models specifically written for the BiMOS process. Simulation is possible at the cell level and, with some difficulty, at the macro level. Beyond that, however, simulation becomes impossible-a direct reflection of the real world. Since a multi-standard TV set may have to conform to over 100 different standards, merely providing the required stimuli would be next to impossible in any sensible time scale. To add to the challenge, not all transmitters conform to the standards, particularly in some developing countries. Video recorders produce nonstandard CVBS. The real world may produce poor quality or weak signals, and frequently introduces reflections. While the designer works to cope with all of these obstacles, it's impossible to provide simulation stimuli to model them for an entire system.

We did nonetheless use simulation to determine the effectiveness of some of the algorithms developed for the picture improvement, confirming that they produced adequate performance. We then implemented them in the hardware.

Prototyping

Prototyping is the most important verification tool, both for the functional blocks and for the entire device. Early versions of TV circuits were breadboarded with real components, using capacitors, resistors, and other components to build a prototype of a block, even before detailed layout. The higher frequencies and greater densities of advanced processes make that now impossible; parasitics, for example, have become a significant issue.

Instead, we fabricated each block in silicon as a test block, with extra pads and test circuits. We exercised these test blocks individually with real-world signals, and then connected them together-using FPGAs for the digital circuitry-to create a model of the entire die, which we then thoroughly tested.

Figure 2 - Digital design flow - front end

The mixed-signal design flow is the top-down variety and uses a number of languages and design tools in the front-end design. The back-end (CAD) implementation makes full use of hiearchy to assemble the cells, blocks, and final chip assembly. Both front-end and back-end flows account for the disparate requirements of the analog and digital circuits.

Analog circuit testing isn't simple. Therefore, even before layout we developed an approach for the test methodology. We have invented an analog equivalent-called ICCQ-to IDQ tests in digital designs. These tests provide current-level monitoring of block functionality deep within the IC. The chip also incorporates a digital register that can quickly carry out a wire-by-wire check. The whole chip can be set to a test mode, making different areas visible to a test system.

As with the digital , we test the entire chip on the wafer before passing it on to assembly as a "known good die."

Digital design

Our company has standardized on VHDL in Europe, and places a strong emphasis on design reuse, maintaining a library of blocks, carefully documenting processes, modules, and roadmaps, and providing suites of tools, all available through the company intranet. Our teams divide every design into functional blocks, with the functionality fully defined. Each block is then assigned to a designer and is treated by the rest of the designers as a "black box." We emphasize right-first-time design; at design reviews, designers must prove that their boxes meet their functional targets.

Design reviews are generally cooperative experiences carried out by a peer group with expertise in the application or the implementation. Less experienced designers are frequently invited to attend design reviews as part of their professional development.

Figure 3 - Digital Design Flow - back end

Philips uses a customized breadboard prototyping system with plug-in daughterboards that contain large FPGAs for either logic or analog/mixed-signal circuitry. Interconnections and probing are facilitated by multiple connectors and test points.

The design review team considers the block as a white box, focusing on those compliances that simulation can't verify, or potential problems-such as power-on lock-up conditions-that simulation might not discover. The reviewers assemble detailed documentation of each issue, helping to ensure that the designer anticipates and resolves them early in the design process. The designer is responsible not only for the design of the block, but also for its simulation and prototyping.

At the end of the development cycle, the designer prepares a design report, in a standard format, that demonstrates how the block meets its requirements and explains the implementation. These reports, along with the source code to facilitate possible future reuse, are posted on the Intranet.

Reuse and redesign

The UOC microprocessor core uses the 80C51 standard instruction set. Memory available includes 3-12 Kbyte x 8-bit internal RAM shared among programs and teletext, on-screen display, and closed-caption page storage. The device also incorporates 32-128 Kbyte x 8-bit one-time-programmable (OTP) ROM, which employs standard transistors for programming to produce denser circuitry that can be fabricated using a standard CMOS process. OTP memory omits from the fabrication process the extra mask steps that inscribe a specific customer's software.

When decomposed into functional blocks, the UOC digital circuitry fell into four classes of roughly equal size: one in which straightforward reuse was possible; one in which the design was good, but needed remapping into the latest CMOS process; one in which some design modification was required; and finally classes of blocks that required a completely new design, such as the memory interface section.

The overall design flow for both front and back ends appears in Figures 2 and 3.

The designers used both schematic capture (using Cadence Design Framework II) and VHDL. Synthesis with Synopsys Design Compiler generated gate-level descriptions for simulation. The designers were responsible for carrying out the simulation (using Cadence Leapfrog) and for confirming that the simulation results matched the function of the block.

Breadboard

We carried out further verification through prototyping. Although a Quickturn system was available, we decided to use our proprietary breadboard system to achieve real-time performance. This approach uses a family of circuit boards, containing embedded resistors and capacitors, that can be tiled through interconnect to match the size of the design. The boards accommodate Altera FPGAs or silicon test chips as well as standard components. The demands of the UOC required some revisions and upgrades to the board, including a new tile layout for the latest generation of Altera FPGAs. We used the RTL developed from synthesis, without the test circuits that are provided for final device test, as input to the Altera place-and-route software, normally with one device for each logic block.

The breadboarding circuit isn't a completely accurate model of the final device. While the board system does run in real time, the performance lies right at the edge of the frequency required for television. Furthermore, clock distribution across multiple boards can make synchronization difficult. Some of the blocks of the UOC lay close to the edge of the capacity of Altera Flex10K 100s used in the boards, which meant that the behavior of successive builds was unpredictable. We partly alleviated this difficulty when we upgraded the target FPGAs to Altera Flex10K 250s, but the depth of logic between registers in the micro-controller sections-such as the "mov" address/data bus-continued to give us problems.

Despite all these issues, the breadboarding system was extremely valuable. It can simulate many real-time problems such as set-up and hold, which cannot otherwise be simulated. It is also good at identifying asynchronous problems. For example, while breadboarding the UOC, one issue resulted from the clock boundary between the memory interface and the display sections of the device. In theory, one of the design reviews for that block should have picked up the problem. Finding the bug at the breadboard stage saved at least one iteration of the silicon-which in itself justified the cost of the breadboarding.

Only at the breadboard stage does it become possible to run very large quantities of real broadcast signals. While the breadboard lacked the full functionality of the final system, it was sufficiently close to serve software development. We maintained copies at two separate facilities where design teams worked on closed captioning and other software developments.

Beyond the bakery

Another copy of the breadboard drove a TV tube for customer demonstrations. The ability to demonstrate the system before it was available in silicon had a double benefit: it gave customers confidence that the system would display high-quality graphics and meet their requirements and it allowed customers to request additional features early enough in the production cycle that they could be serviced without incurring significant redesign costs.

We used Cadence Silicon Ensemble for layout and stored the die as GDSII, then carried out a standard series of verification and checking exercises (such as LVS). We developed in-house rules for scan-session checking. A top-level test bench generated TV RGB signals and TV frames for Leapfrog simulations; for back-annotation we used this output as well as the output from static and dynamic timing analyses.

To reduce the final test time, we put great effort into considering the final testing of the device from the earliest stages of design. We tested the on the wafer and passed only known good die to assembly. After mounting both die, we put the package through further testing, although some of this can take place on both concurrently. At this stage we aimed for a failure rate of 2 percent or less, attributing all failures to the assembly phase.

The first silicon for both the analog and digital components of the UOC was sufficiently functional to be shipped to customers for them to begin their own software development without waiting for the final modifications. Most of the world's television manufacturers are evaluating the product, with some companies committed to designing it into products that will start shipping in the near future.

The final version of the UOC will burn the customer's software into the OTP memory, which, in itself, is a significant move. This allows programming to take place on fully packaged die, rather than requiring a final mask layer.

Developing the UOC provided us with a great deal of valuable experience. When the project started, the design teams in Nijmegen, The Netherlands, and Southampton, England, were part of separate business groups. Developing the business case and then defining the product was a true joint effort across organizational boundaries. Although the interface was strongly defined, communication between the groups continued during the product design cycle and contributed to the ultimate success of the project.

Chris Hopwood is UOC product development manager at Philips Semiconductors, Southampton. He joined Philips Semiconductors Southampton in 1985 as an IC designer, then became project leader in 1989 and has been responsible for a wide range of ASIC applications projects.

Andrew Vagg, IC design manager for TV products at Philips Semiconductors in Southampton for the last three years, joined the IC design group in 1984. As IC designer, project leader, and most recently, product manager, he has been involved in many consumer IC applications.

Pete Hawkins is an IC architect at Philips Semiconductors in Southampton. After working at Siemens Plessey Systems since 1988, he joined Philips as an IC designer in 1996. In 1998 he moved into an IC Architecture role. His areas of expertise include data broadcast acquisition, embedded micro-processor cores, memory interface and graphics engines.

John Somberg is the development and application manager for basic video processing at Philips Semiconductors in Nijmegen. He joined Philips in 1985, serving initially as an IC designer for TV-IF circuits, then becoming One-Chip project leader in 1990. Since 1998, John has been responsible for the development and application crew for TV signal processor ICs.

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