With big-picture issues such as hardware/software codesign, IP reuse, and block partitioning plaguing system-on-a-chip (SOC) design, it's easy to lose sight of a concern as commonplace as signal integrity. However, technology scaling, higher clock frequencies, and increased levels of integration have had a substantial impact on noise and signal integrity, with more factors coming into play than ever before. While circuit behavior was previously determined by parameters such as supply voltage, temperature, and transistor behavior, the design of 0.16-ým technology and below has made the interconnect an increasingly important consideration in determining system performance. Faster clock and signal edge rates result in increased signal coupling, while scaled-down power supply voltages have led to decreased noise immunity in the interconnect.

Excessive noise can result in seriously reduced yields or even chip failures, often causing designers to over- design in attempting to compensate. Signal crosstalk can cause glitch-related functional failures, which are often insidious and difficult to detect. Wide variations in signal delay and slew-rate due to signal coupling can result in catastrophic speed-related errors. Failure to discover signal integrity problems can lead to a faulty prototype, costing weeks of valuable time in getting a product to market.

Today's tools and design methodologies tend to focus on validating designs for timing and power requirements. However, as noise becomes a serious issue in ultra-deep-submicron (UDSM) designs, methodologies will need to incorporate signal integrity analysis into every stage of the design process.

Considering noise in digital designs

In digital design, a range of analog voltages can be defined in terms of a logic 1 and a logic 0. As long as the analog voltage falls within a certain valid range determined by the circuit's noise margin, the system functions properly. However, noise introduced into the circuit through mechanisms such as signal coupling, simultaneous switching, and substrate coupling can cause the voltage to deviate from a stable value and thus affect the circuit's functionality.

Noise has always been an important design parameter in analog circuit design, where sources of noise are associated with physical effects such as shot noise, thermal noise, and flicker noise. In digital design, however, signal integrity has been less of an issue because digital circuits are immune to most of the damaging effects of noise.

As the industry moves into 0.16-ým process technology and below - and more functionality is integrated into multi-million gate SOC solutions - noise is becoming more of a concern. Finer technologies have led to aggressive scaling of the interconnect in lateral dimensions with relatively unchanged vertical dimensions. The result is stronger capacitive coupling between adjacent wires. At minimum spacing, more than 90 percent of a wire's total capacitance can be attributed to capacitance from its nearest neighbors on the same metal level (see Figure 1).

System requirements lead to greater performance demands, which translate to faster clock rates and signal edge rates-and increased signal coupling between nets. Additionally, as designs become more complex, global interconnects become longer with more opportunity for a signal to be affected by noise or for a signal to dissipate. Subsequently, reducing the voltage headroom in a designer's workspace is a direct consequence of reducing supply voltages for power considerations. Low-threshold devices are being used for performance reasons. But, unfortunately, they result in devices that are more susceptible to noise.

The projected increase in design complexity over the next several years will dictate significant improvements in design methodology and designer productivity. One approach to addressing productivity has been IP reuse within an SOC design, with models to verify timing and performance issues. Unfortunately, there are no established standards in place to define noise analysis and signal integrity parameters for an IP block, making it difficult to verify signal integrity before prototype.

Effects of interconnect crosstalk

Noise caused by interconnect capacitive crosstalk potentially produces two deleterious effects in any given digital design. First, it can cause a glitch in a normally static signal, which can in turn transiently destroy the logical information at that node in the circuit. This may result in a functional failure if an incorrect machine state is stored in a latch. Second, in static CMOS, crosstalk causes wide variations in wire delay, which can in turn cause speed-related errors (see Figure 2b).

Figure 1 - Capacitance runs amuck

The trend in metal-1 capacitance: as technology scales down, capacitance escalates.

Falling and rising glitches can precipitate false switching of a gate at the receiving end of the victim net. Overshoot and undershoot glitches can cause current flow through the diode between the drain and substrate in the driver gate. Capacitive crosstalk can also cause a variation in the delay on the victim net when the aggressor nets coupled to it are also switching (see Figure 2c). The delay on net B can vary significantly, depending on the direction of the switching signal on nets A and C relative to the signal on B.

In analyzing wave forms, the designer may assume that the worst-case delay scenario occurs when the lines A and C switch simultaneously, but in a direction opposite to that of the signal on net B. The formula 2 x Ccoupling is often used for a simple worst-case analysis. In reality however, those signals arrive at different times and travel with different edge-rates within a circuit (see Figure 3a). This can cause the signal on a victim net to be non-monotonic; the signal goes across the receiving gate's threshold and causes the receiver gate to switch (see Figure 3b). The traditional formula, then, doesn't capture this scenario-a situation which must be carefully considered during the design process.

Traditional tools and methodologies

Until now, tools and methodologies have been concerned with validating a design to ensure functionality, timing, and power requirements. The increasing effect of the interconnect on path-delay has led the ASIC design world to grapple with timing convergence between the synthesis and post-layout stages of the design flow. Unfortunately, the important issues of noise and signal integrity haven't yet become an integral part of the mainstream design flow.

Today, most designers analyze their designs for crosstalk based on coupling capacitance extractions or by using vector-based simulations. While coupling capacitance does provide a first-cut understanding of potential crosstalk problems, it can be quite misleading unless total net capacitance, drive strength of devices, and sensitivities of receiver circuits are accounted for. Testing usually comprises the use of vector-based simulations to create worst-case crosstalk scenarios. However, as illustrated in our example, it isn't always easy to determine what vector set forms the worst-case crosstalk condition. On the other hand, static analysis can be overly pessimistic unless it incorporates some information about timing and functionality of the circuit.

Figure 2 - One good glitch deserves another

(a) Couple lines A, B, and C. (b) Glitches caused on victim net B due to capacitative coupling from aggressor net A and C. (c) Signal direction on nets A and C can significantly effect the delay and slew-rate on net B.

In full-custom designs, with somewhat longer design cycle time, designers typically address signal-integrity issues by optimizing specialized signals. Nets such as memory addresses and data buses are designed through careful, time-consuming modeling and optimization of each interconnect, shielding signal paths with power and ground planes, and verifying with time-domain simulations. However, this process is far too taxing on both time and resources to be feasible for more general cases.

In the ASIC design flow, crosstalk has only recently become part of the design methodology. While more designers are dedicating attention to crosstalk analysis, there are several issues that still need to be faced: the often-overlooked timing effects of noise; managing data generated with crosstalk analysis tools and converting it into useful information; and test generation for crosstalk effects-particularly for circuits with multiple clock domains and asynchronous designs.

Crosstalk analysis tools can't deal with the complexity of designs and with the issues of data management. Today, these tools require a flat analysis approach within the hierarchical process, in order to access all of the blocks. In addition, if an imported IP block is used, all relevant data required for the analysis may not be available from the IP vendor.

Methodology evolution

As we move beyond 0.16-ým process technologies, ASIC and custom-design flows are merging into a single flow for SOC. This flow must consider chip complexity, true hierarchy, use of IP blocks, noise issues, and signal integrity in each phase of the design. To properly address these issues, Lucent has brought to bear its experience in both hierarchical design flow and SOC design. This comprises the development of semi-custom and full-custom design techniques, as well as the design of analog, processor, and memory block elements.

Figure 3 - Coping with coupling

A simple worst-case analysis may not reflect the case when signal arrive at different times and travel with different edge-rates within a circuit-the signal on victem net (b) being non monotonic.

To address the problem of signal crosstalk, we have incorporated analysis tools into the SOC design flow. Specialized signal paths such as memory address lines and data busses are optimized using Laplace equation solvers, which achieve noise immunity and robustness to process variations while minimizing delay and power consumption. This is usually done early on in the design cycle, as soon as process-technology specifications are available to the designer.

For example, in sub-volt DSP designs, noise is a critical concern. Proactively, we use design guidelines to ensure that most of the crosstalk problems are addressed early in the design process, either at the floorplanning or place-and-route stage. These guidelines specify rules for spacing between metal lines and signal shielding for critical signals like clocks and busses. Subsequently, post-layout verification yields a manageable number of nets that require designer intervention. Signal integrity verification tools are based on state-of-the-art model- reduction and linear network analysis techniques. Noise effects due to capacitive crosstalk, charge-sharing, leakage, and power distribution are considered in the signal integrity analysis. These tools provide information about signal glitches and delay variation due to crosstalk effects, while taking into account the noise sensitivity of the receiving-end gate.

High-accuracy layout extraction tools generate enormous amounts of data that is used for timing, power, and signal integrity analysis. Lucent has developed techniques to translate this data into information that the designer can use to localize problem areas in a design. The data analysis and representation techniques used by our tools were developed by Bell Labs statisticians for data mining, then tailored to address signal integrity.

As the SOC-design flow evolves, we are bringing together tools and design processes in-house and partnering with external tool vendors so that signal integrity concerns are addressed. Today, there are multiple tools for verification of various performance issues, but no integrated solution that can pass information between the different tools and the various levels of hierarchy.

Lucent's solution has been to integrate parts of the design flow through a suite of software that uses a web-based computing paradigm. By using a web-interface with high-peformance CPUs on the back end, designers have far more compute power than would be available at their desks. The interface forms a web-based layer over the tools and compute servers such that the system is available via the intranet to the entire design community at Lucent. The web interface also facilitates a very short learning curve since the user doesn't need to understand the software and hardware behind the interface and only requires familiarity with a standard Internet browser. In addition, we are able to better manage issues such as task management, data flow, memory, network traffic, and parallel processing.

In order to manage the level of complexity of an SOC design, the designer must make a fundamental assumption: At the time of chip-level assembly, each of the component blocks are inviolate. This means that each block needs to be characterized and verified for parameters like power, timing, design rules, and signal integrity. Therefore, each block can be included as a component in the next higher level of hierarchy and its pre-characterized parameters should be usable for characterization and verification at that level of hierarchy.

Figure 4 - SOC today and tomorrow

New, streamlined methodologies will be required to meet the demands of deep-submicron design and SOC integrations.

The requirement of inviolateness imposes additional constraints on the design process of the block. For example, crosstalk considerations may require restricting top-level routing from interacting with routing within a block. If interaction is allowed, the subsequent effects must be accounted for during block design and provided as a specification for the next level of hierarchy.

Verifying each block and the top-level interconnect independently are integral parts of ensuring signal integrity in an SOC-design flow. As each block is designed and laid out, iterations may be needed to check that it meets its timing and noise specifications. The additional iterations will ensure that a design team meets its timing and signal integrity specifications. When a higher-level block is assembled from a set of blocks whose specifications are known, the same process is needed to make sure that this block meets its design specifications.

An SOC-design methodology that effectively considers signal integrity must approach noise management and noise budgeting in the same way we now budget for timing-from the point of view of both design and verification. A range of tools, models, anddesign processes that incoporate signal integrity metrics into every stage of the design process are being developed. Some of the issues that are addressed include noise sensitivity, noise injection, layout rules, and metal layer utilization.

Future directions

Beyond developing a signal integrity flow for SOC design, significant work needs to be done in-house, with third-party IP providers, and EDA vendors to standardize IP models for signal integrity analysis and verification. There has been a great emphasis in the industry to standardize issues such as timing analysis and power analysis. Unfortunately, there have been no similar efforts for signal integrity. The seriousness of design complications resulting from signal integrity requires the industry to develop standards, languages, and interfaces within our IP models and our tools to represent signal integrity data-and to pass that data between different levels of the design hierarchy (see Figure 4).

As designs become more complex and move to sub-0.16-ým process technologies, signal integrity is becoming an increasingly important and thorny issue. Evaluating the challenges and formulating a complete strategy that integrates into current design flows will help designers meet time-to-market windows, without sacrificing the performance and reliability of their chips.