Motivated by competitive pressures to deliver better, faster, cheaper chips, leading microprocessor makers aremoving as rapidly as possible to 0.18-ým technology and below. Unfortunately, shrinking feature sizes demanded by the relentless microprocessor marketplace are beyond the capabilities of even the most advanced lithography manufacturing equipment today. As feature sizes go below the wavelength of light used by advanced optical lithography equipment (248 nm, today), pattern distortions such as line-end pull back and line-width variances are increasingly common.

Next-generation 193-nm lithography equipment and resists are still immature; 248-nm exposure wavelength will be used for the mass production of 0.15-µm technology devices and still present the most likely lithography solution for 0.13-µm technology. In the near future, the printed features will shrink to half of the exposure wavelength. Therefore, achieving pattern fidelity and process latitude for these extreme sub-wavelength design rules will present significant challenges to both designers and semiconductor process engineers.

Even the smallest distortions in gate-channel length can be particularly problematic to makers of high-performance microprocessors. Transistor performance is strongly dependent on the channel length across the entire transistor width. Distortions of small aspect-ratio gates have a direct negative impact on electrical performance and yield; such deviations have significant impact on microprocessors' success. For these products, speed means everythingýnot the least of which is the ability to command higher prices (see Figure 1).

When Advanced Micro Devices (AMD in Sunnyvale, CA) set out to produce an advanced 0.18-µm process technology, it was clear that maximizing speed would make the difference between success and failure. We knew that eliminating subwavelength distortions, particularly on performance-critical transistor gates, would be essential. Some of the subwavelength distortions can be eliminated by process optimization. However, we have found that resolution enhancement technology (RET) in the form of optical and process correction (OPC) and phase-shifting masks (PSM) proved key to bridging the gap between the capabilities of our 248-nm lithography equipment and the feature sizes required for our design.

The quest for faster chips

Today, there are three common means to elevate performance levels for a given microprocessor design. During design, you can improve the layout to optimize the circuit design. This is probably the most powerful approach to improve the performance of a microprocessor, since new design architectures can significantly improve the speed of a microprocessor in a given technology. Unfortunately, once the design has been finalized, the manipulations and checking required for significant design modifications are far too slow and labor intensive to be practical for our complex circuits and narrow market windows. Consequently, major revisions to design architecture are only made once every two years or so.

Alternatively, you can uniformly reduce circuit feature sizes. Shrinking a design in this way saves design time, since often the same basic design can be used with only minor circuit modifications. The improved circuit performance and increased number of die per wafer mean that wafer shrinks are done as often as possible. However, fabricating such small features on all layers requires lengthy overall process development and a tremendous capital investment, which means we can only shrink the design once every 18 to 24 months.

Figure 1 - Speed versus pricing

For microprocessors, arguably more than any other product today, pricing is a strong function of speed. As a result, minimizing gate channel length (which governs overall speed) is a high priority for these products.

A more pragmatic means to glean speed from a design, allowing for a continuous improvement in microprocessor speed on a month-to-month basis, is to shrink only the transistor gate-regions. Yet, even this seemingly simplistic solution presents complications today. Reducing transistor gate length has significant impact on overall performance, is easy to implement during design, and requires minimal process improvement. The merits of "gate shrink" have long been understood, making it a very popular technique for improving IC performance. Today, however, shrinking the gates of a 0.25-µm or 0.18-µm design results in transistor dimensions well below the wavelength of advanced 248-nm stepper equipment. Subwavelength distortions such as corner rounding, line-end pull-back, and biases between transistors on different pitches—also called the "dense-iso" bias—can undermine any expected performance gains from such a gate shrink.

To successfully realize subwavelength geometries, lithography and design engineers employ resolution- enhancement techniques that serve to extend the capabilities of existing lithography equipment. Applying strong PSM techniques to the gate regions of polysilicon layers makes it possible to pattern both isolated and dense gates at critical dimensions as small as 100 nm in resist using 248-nm tools. Like traditional binary masks, phase-shifting masks exhibit optical proximity and process effects that cause the printed wafer pattern to deviate from the desired pattern. For example, PSM designs that haven't received OPC are prone to rounding at the junction between phase-shifted and non-shifted regions due to the combined effects of mask fabrication and dual exposure lithography.

The coherent illumination used to expose PSMs leads to increased dense-iso bias. In addition, subwavelength distortions that result in non-uniform channel length across the width of transistor gates can directly impact device performance. Simple gate shrinks aren't enough anymore, and even phase-shifted patterns must be OPC-corrected. Thus, to ensure gate resolution and control as well as to eliminate pattern distortions, it's necessary to combine PSM with OPC techniques.

Homing in on optimal solution

In order to realize a reduced-gate version of our 0.25-µm processor, we used a combination of PSM pattern generation and OPC on the poly-gate regions. Our design is a two-mask implementation in which a phase-shifted mask defines the transistor gate-regions (identified by the intersection of the poly and active patterns) and a standard binary mask delineates field poly. As part of our work, we experimented with different mask pattern derivations and explored alternative design rules. All simulations, layer definitions, PSM assignments, and OPC corrections were performed using Mentor Graphics' Calibre RET software tools.

To better understand the capabilities of RET for our purposes, we experimented with different implementation options. Specifically, we assessed three different sub-248-nm design rules, various PSM oversizes, and OPC-correction versus non-correction. First, we fabricated a two-mask PSM without applying OPC. For this experiment, we extended the phase-shift dimension by 125 nm beyond the edge of the active region, and placed an original 250-nm pattern, as well as 175-nm and 150-nm direct shrinks on the same reticle. As expected, results of the combined exposure of field and gate masks reveal adequate integrity of the 250-nm pattern, but significant distortion of the 150-nm pattern. Of particular concern to us was the encroachment of field poly into the gate area, which makes control of the gate dimension of short-aspect-ratio transistors very difficult (see Figure 2).

In the attempt to improve upon pattern fidelity and gate-sizing control, we next explored the effect of introducing model-based OPC as well as the impact of relative sizing of gate and field masks. During the initial basic phase-shift assignment, it's possible to vary any number of parameters — including the amount by which the PSM gate mask extends beyond the gate region as well as the sizing of the chrome pattern of the complementary-field poly-mask. We knew that PSM oversizing was particularly important for our purposes because it corrects for phase effects extending beyond the active region, which, in turn, can cause non-uniform channel length across the width of a given transistor. Because of the significance of PSM oversizing in the quality of correction and device performance that can be achieved, we elected to focus our experimental efforts on this parameter.

Figure 2 - Subwavelength distortions

As critical dimensions are reduced below the wavelength of 248nm stepper equipment, distorted geometries result.

We first used the Calibre tools to generate the initial phase-shift mask layers, a PSM operation to define gate poly, and a binary mask for the field poly. We next performed optical proximity corrections on the phase-shifted layers. Using the Calibre OPCpro tool, we performed model-based OPC. On a 175-nm pattern, we found that more thorough model-based OPC-corrected images alleviated much of the distortion observed in the uncorrected image, in particular all evidence of line-end shortening was eliminated. On OPC-corrected images with only a small amount of PSM oversizing, some distortion of the gate CD still remained (see Figure 3a). As we increased PSM oversizing, we found that the pattern could be completely straightened out (see Figures 3b and 3c). OPC served to correct CDA bias and line-end pullback effects.

Using this combination of RET techniques, we were able to successfully produce transistor gate lengths of less than 175 nm using 248-nm lithography equipment. Recent experiments suggest that gate lengths down to 100 nm will be achievable in production with this technique. However, it must be recognized that, although this PSM technique allows for aggressive reduction of transistor size and increases the microprocessor speed, it doesn't affect the overall size of the circuit and hence doesn't improve the number of die-per-wafer.

Tools that make it happen

RETs, because they enhance the printed image, have traditionally been seen as the domain of the lithography group. However, any changes to the final printed image may affect other process modules. Designers need to ensure that the RETs don't have any unintended or adverse impact on yield. Furthermore, RETs are implemented by the mask generation/tapeout group. In order to successfully implement RETs, it's therefore necessary to have a cross-functional team with members of lithography, process integration, and mask generation groups.

The initial stage of the evaluation may be performed by the lithography group, and the main focus is on improvements in pattern fidelity and lithography-process latitude. However, once promising initial results have been obtained, it's necessary to ensure that the RET methodology chosen is compatible with current mask-generation procedures. The mask-generation process has long included data manipulations designed to improve the manufacturability of designs. If done properly, the implementation of RETs can allow consolidation of some of these ad hoc practices in a more streamlined process.

Implementing complex RET techniques on a 20-million transistor, 7th-generation microprocessor design was a daunting task at the outset, and we gave careful consideration to the appropriate RET implementation system prior to undertaking this work. We knew that our system would need to be capable of deriving the PSM layers, including the oversizing and other manipulations required for optimal results.

Figure 3 - OPC correction versus PSM oversize

By increasing the amount of PSM oversize plus OPC, it's possible to correct all subwavelength distortions on a 175-nm gate using 248nm lithography equipment.

Performing OPC and PSM on a design requires that these two operations be carried out simultaneously in software. Simulating results productively and accurately also proved critical to assessing the alternative implementations. Of course, the complex computational task of PSM and OPC manipulations, simulations, and verification had to be performed within a minimal time frame, so turn-around time was also an important consideration. In considering turn-around time, we were concerned not only with software run-time, but data expansion and mask manufacturing time as well. Unless data expansion and flattening are limited by the software, downstream tools can be slowed down or rendered inoperable by memory limits or sheer data volumes.

Additional complications

We also had technical concerns. Model-based OPC has never been a simple technology to deploy, but today it's even a more complex problem when coupled with PSM. To effectively use these techniques together, we need to ensure that algorithms for PSM and OPC will work together as simulated. In addition, the software must generate the actual target layer—modify the idealized design database to reflect what the designers actually want to see on the wafer. Concurrent generation, simulation, and correction of all three physicallayers (the theoretical target layer, the phase-shifted layer, and the field layer) maximize the solution space of possible configurations, enabling a more productive and optimized implementation.

Another complication of using OPC and PSM together is differing mask error enhancement factors (MEEFs), a term that compares the sensitivity of a printed image's dimensions to variations in the actual mask dimension. In short, different MEEFs apply for phase-shifted and non-phase-shifted regions, and OPC algorithms must comprehend this difference in order to adequatelycorrect all of the poly layer geometries.

We found the Calibre tool suite well suited for our requirements in a RET implementation system, a system fully capable of performing complex phase shifting and field-layer derivations, OPC corrections, lithography simulations, and design-rule verification required for our design. Early on, we compared simulated aerial images to actual SEMs of resist patterns, and found that the simulations predicted wafer results with extreme accuracy. Turn-around time and data expansion results with the Calibre tool suite were also quite good (see Table, p. 51).

Running the software on a 300 MHz Sun Ultra Server with 1GB of RAM, we achieved very acceptable turn-around time. Even when applying data processing-intensive model-based OPC and PSM simultaneously, simulation execution time was less than 16 hours (on five 360-MHz CPUs). Heuristics within Calibre software that improve the hierarchical efficiency of the layout helped to keep data expansion within reasonable limits.

Using the tools and our existing 248-nm lithography equipment, we demonstrated: optical extension via RET offers a viable means by which to achieve 175-nm design dimensions; gates down to 100 nm can be patterned today using currently available processing technology; 70-nm gates will be achieved with the newest 193-nm equipment. We successfully performed OPC and PSM on a complete state-of-the-art microprocessor design in a very reasonable amount of time. Moving forward, even as 193-nm equipment comes on line, these techniques will remain critical enabling technologies for developers of advanced subwavelength ICs.