The researchers at IEDM are looking at alternatives to the existing planar structures and the very real optical limits to reduced dimensions. Some of the alternatives to the flat device on silicon are vertical devices with gate lengths determined by the thickness of atomic layers, or the effective gate length determined by a self-aligned photolithography process. The new structures address some of the problems of very small devices-short channel effects, subthreshold operation, and device leakage. A vertical device structure makes the gate available on both sides of the conduction channel, allowing even low-threshold devices to shut off completely.

Before it can taste the fruits of the researchers' labors, the designer community must change its design philosophy. The tools for designing the "super chips" must address many new issues. Already, even at the 0.25-ým process geometries, designers are finding that the available silicon is more than enough to accommodate their designs. In a complete reversal of priorities then, the job is no longer to squeeze as many gates into as small a space as possible, but to include all of the desired and necessary functions in the design. A number of designs have shipped with a ring of white space inside the pads, because the number of pads defined the die area and the designers lacked the time to add logic. As the designs become even larger and more pad-limited, expect to see more ICs shipped with white space, particularly as companies run out of the design and verification resources necessary to add capabilities to the designs. Some consultants have noted that their customers haven't violently objected when the final design ends up with more than 50 percent more gates than the original estimates. The client companies have decided that total functionality is more important than gate count, especially when the die size, and therefore the cost of the part, may not have changed from the original estimate.

In fact, the incremental cost of additional gates may be negative. For example, adding 10,000 gates for testing functions may reduce the cost of testing enough that the total cost of the part is lower than the original cost. Including separate address decoders for each memory may increase throughput enough to allow a slower processor, permitting looser timing and saving power at the same time. When the silicon manufacturers consider a 1-cm2 die as relatively manufacturable, the total quantity of possible gates approaches 10 million gates. Therefore, adding 0.1 percent more gates is negligible in terms of available silicon.

The continuing increase in IC performance is driven by faster devices and greater circuit complexity. As clock frequencies increase up to and beyond 1 GHz, the number and types of interactions within the circuits will increase in proportion to the frequency. The experiences of the pioneering companies that moved to 0.25 ým demonstrated that increased circuit speeds and complexities generate new problems and failure modes that weren't significant in the previous process generation. Even though the changes in design and processing technologies contribute to the faster and more complex ICs, major problems will surface in those areas where physics intrudes-along with its ugly features. No one has figured out how to even partially repeal the laws of physics, but the next few generations will challenge the limits of device knowledge, technology, and the physical characteristics of the base materials. The physical laws can't be broken without causing irreparable damage to something in the IC.