As an example of the increased attention and concern the EDA companies are showing, I was recently involved in a panel discussion on the topic of design closure. The problems of design closure revolve around the need to solve a number of independent effects simultaneously. In addition to the primary problem of timing closure, the next generation designs will need to address power, noise, thermal, EMI, and current density in the layout to ensure a working, reliable part.

The panel members described some of the trends they currently observe and noted the overall increase in design complexity, and the corresponding decrease in time to complete the job. The next generation of processes will have mask sets going for over a million dollars, so even one iteration is unacceptable. The newest designs are using more cores, both internal and third-party, to help in the front-end of the design process, but cores exacerbate the physical verification problems. Even when the design is on an esoteric process like SiGe, the essential needs for design closure are parasitic extraction and analysis. As the clock frequencies continue to increase, the timing budgets become smaller, allowing even fewer margins for error.

To address all of these issues, one school of thought is to add more tools to the chain. By adding point tools, the designer can increase the accuracy of the extracted data to get a better analyses on the resulting designs. Our January Focus Report on physical verification tools looked at some of these types of extraction and analysis tools and discussed the need for greater interoperability amongst those tools. This alternative — to retain the existing methodology while adding in new tools — also requires the addition of more staff to handle the physical verification tasks. Few designers and CAD people understand the data and analyses of the "other" effects, so domain experts become necessary.

Another alternative, discussed in our February Focus Report on RTL floorplanners, addresses the design closure issue by improving the accuracy of the starting constraints. In this context, the designer is most concerned with critical timing aspects and therefore best able to define the constraints at the RTL. Then, the design team can use the constraints throughout the design process. Additionally, the pre-layout data and the post-layout data rarely, if ever, match. The development and application of limits at the RTL can lead to the possibility of an over-constrained design and may lead to a congested and difficult layout if the RTL doesn't map well into the available libraries.

This month, we are addressing the final aspect of the implementation of timing and other constraints at the physical level. The nature of the placers and routers is going to be very interesting, as the tools address the multiple challenges of the latest IC processes. Not only do the tools have to face the growing number of analyses, but geometrically increasing numbers of active and passive components within the IC design must be addressed as well. The emergence of 10 million gate ICs is a significant event — these quantities will become routine in the next era of designs and processes. The semiconductor makers continue to increase the number of active devices per die, forcing the next generation of physical design tools to address more issues all the time.

The next generation of IC designs will be even more difficult to finish. Already, the foundries are starting to talk about releasing the 0.13 ým processes into production. The next generation of processes will have quite different characteristics from the 0.25- and 0.18-ým technologies of today. The newer fine-line processes will have more layers of interconnect, with new dielectric materials and considerably different characteristics from the CMOS of today. The interconnect will be the dominant design feature of all new ICs and will probably require even more analyses and constraints than those of the current state of the art. Check out our report and see what's happening in the the final part of the IC design process.