United Business Media EE Times


Search

HOMEMARKET INTELLIGENCE UNITFORUMSDESIGNNEW PRODUCTSCAREERSBLOGSCONTACTEVENTSSIGN UP!RSSMost Popular contentTrusted Sources

 

Feedback

Mask costs contrasted

To Tets Maniwa:
Thanks for your excellent article on ASIC design ("Focus Report: ASICs Today," ISD Magazine July 2000 p.93). You mention in the article that a mask set costs a million dollars, and minimum volume is one million for an IC design using the latest process geometries. Your point is that ASIC vendors are all chasing the few IC designs that meet these criteria.

I think the real economics of doing SOC development is much different. Most foundries (TSMC, UMC, Chartered) quote a price of approximately $10,000 per mask. With a typical 12-mask 0.25-ım process, the mask cost is approximately $120,000, with perhaps an additional $10,000 dollar for a probe card. Basically, for COT process the NRE costs are an order of magnitude lower. Most foundries also provide multi-project wafers (MPW) for approximately $25,000 in NRE for prototyping. Most foundries have MPW shuttles going every week. IP vendors can even get into MPW wafers for free if the IP is considered strategic.

How do you reconcile these two widely varying numbers for SOC costs between ASIC (gate level sign-off) and COT (GDS-II sign-off)? The difference in NRE can be explained by the cost of providing place-and-route services, which is provided by the ASIC vendorınot the COT foundry. I believe most of the cost of place-and-route services is in the manpower. Sometimes ASIC vendors also bundle cost of their IP into the NRE.

I believe design managers can significantly reduce the cost of developing a SOC by investing an in-house place-and-route capability and using a COT foundry for manufacturing.

Wishing you the best in your new role at EEdesign.com.

Bejoy G. Oomman
Genesys Testware
Fremont, CA

Tets Maniwa replies:
For a 0.25-ım mask set, the cost is only about $10,000 per layer. For the very advanced processes, 0.15-ım or 0.13-ım, the mask costs will be closer to the million-dollar range. Most of these masks will require OPC and phase shifting, which more than doubles the cost. In addition, the number of layers will increase from the 12 in the 0.25-ım process, to over 20 masks in the 0.12-ım process. Going to a foundry with a full COT flow will save you the other NREs, but will not make a significant difference in mask costs. The ASIC vendors donıt have a lot of padding in the cost of the mask set, but do have a lot of other costs that are passed on to the customer as a part of the total NRE.


Send electronic versions of press releases to news@isdmag.com
For more information about isdmag.com e-mail webmaster@isdmag.com
Comments on our editorial are welcome.
Copyright © 2000 Integrated System Design Magazine

  Free Subscription to EE Times
First Name Last Name
Company Name Title
Email address
  Click here for your Free Subscription to EETimes Europe
 
CAREER CENTER
Looking for a new job?
SEARCH JOBS
SPONSOR

RECENT JOB POSTINGS
CAREER NEWS
SRC Expands R&D Centers
The Semiconductor Research Corp has added a new center to its university R&D efforts.

For more great jobs, career related news, features and services, please visit EETimes' Career Center.


All White Papers »   

 
Education and
Learning


Learn Now:












Home | About | Editorial Calendar | Feedback | Subscriptions | Newsletter | Media Kit | Contact | Reprints|  RSS|   Digital|  Mobile
Network Websites
International
Network Features




All materials on this site Copyright © 2009 TechInsights, a Division of United Business Media LLC All rights reserved.
Privacy Statement | Terms of Service | About