As the ASIC industry moves into an ever-greater proliferation of processes, the challenge of reporting on the different offerings becomes a Herculean task. The ASIC industry is changing into a Hydra before our very eyes, a many-headed monster. The base CMOS process has migrated from 0.25 ým to 0.18 ým, to 0.15 ým, and even to the 130-nanometer line dimensions in this past year. Not only are processes proliferating at an ever-growing rate, but the number of processing modules on each geometry is also increasing. On top of the base CMOS process, many fabs offer additional processing steps to enable analog, DRAM, SRAM, Flash, and higher voltage I/Os. For geometries at 0.15 ým and below, the process may have to diversify into multiple versions to handle the demands of high densities, high speeds, and low power.

The minimum dimensions represent the smallest line widths for the transistor gates. The other critical dimensions are following along, although the other feature sizes are not changing as rapidly as the gate length. The feature spacing for large objects is down to a micron, and the metal pitch is below 0.35 ým. As the metal spacing and metal width shrinks to accommodate the new, finer process geometries, the number of metal layers has to increase to handle increased device complexity and the growing quantity of interconnect. Even though the individual devices are getting smaller and the metals moving closer together, the average length of interconnects, paradoxically, is increasing. Larger numbers of connections are needed for larger blocks and longer routes require internal lines that may, in fact, exceed the length of the total die.

As time goes by

The number of gates possible in a 150-nm process is about 100K gates per mm2, resulting in a 10 million-gate design fitting into a square centimeter! The advantages of a high-density process are greater gate counts, higher speeds, higher reliability, and lower power per gate than the "fat" processes - assuming supplies and thresholds don't go so low that leakage becomes a major factor. The circuit densities will vary greatly, however, depending on the design intent. A design optimized for density is very different from one optimized for speed or another one designed to minimize noise and signal integrity issues.

A very large chip might have many libraries of standard cells, each optimized for different parameters. The high-speed, high-power library is for data paths, the high fan-out parts for buses and other large structures, low-speed (and lower power) for control logic, and other libraries for special functions like arithmetic or test. Any individual design may have a spectrum of optimizations: low power and high density, low power and low noise, and so on. If we multiply out the matrices, we will have over a hundred variants to a single generation of minimum gate dimensions.

Why would anyone go to all of this trouble to create the myriad possible variants for a wafer process?

Answer: to integrate more functions on a single chip, ultimately resulting in a system on a single chip. The reason the semiconductor vendors are in this treadmill-like race is obvious. The latest fabs require high volumes of wafers processing through them to make any money. But it takes money to guarantee revenue and the bottom line. One vendor recently told ISD Magazine that the magic number for ASICs is one million - a number with significance on various fronts. One million represents the number of dollars for a mask set, the minimum number of gates worth integrating onto the smallest manufacturable die, and (probably) the minimum quantity of parts that need to ship annually to meet revenue demands.

Moore of Murphy

In this rarefied atmosphere of high volumes and start-up high costs, the number of potential customers for ASICs drops to only a few hundred companies in the world. Obviously then, the competition for the miniscule number of customers is fierce - the ASIC vendors and the foundry jockies need to develop and maintain incremental technical advantages over their competition. To get an edge on the "other guys," companies push to get the next generation process technology into manufacturing at the earliest possible date, and start delivering information on device characteristics to their favorite customers as soon as the device - and process people - can develop a working model. The data are very preliminary, so the information is only presented to the few companies who are actually getting ready to start a design in that particular process technology.

According to Murphy's law, whatever change is most likely to cause problems, undoubtedly will. The important or necessary parameters require new models and the design gets shoe-horned into a set of device parameters that aren't the same as they were at the starting point for the design.

We may have actually gotten to the point where the next process shrink is not for faster parts, but for higher gate densities per mm2. In the 0.25-ým processes, gate delays were in the 1-nanosecond range. The high-speed versions could get you under 500 picoseconds. The latest 0.15-ým gates have propagation delays in the 100-ps range, and transition times in the 10-ps to 20-ps range. Even when the delays are adjusted to accommodate set-up and hold times, a single-level logic only needs slightly more than 100 picoseconds. This is expected to drop to below 25 ps in the 100-nm generation - due in about 2 years.

Speed limits ahead

The 0.15-ým IC shouldn't have too much trouble keeping up with a 500 MHz clock, as the total delay for a block of logic with 3 levels of gates is "only" about 500 ns. The gate delays for 3 levels of gates in a 100-nm process would be about 100 ps, and those speeds still fast enough to keep up with the 2 GHz clocks projected for 2003. Today, only a few ICs are running at this clock speed. In fact, most designs are running at less than 200 MHz.

Just as the design intent has shifted from squeezing as many gates as possible into the available space to achieving the greatest functionality in the design time available, the device speeds may have crossed a threshold where faster parts don't actually offer that much help to the designer. Even though the propagation delays are becoming totally dominated by the interconnect, the emphasis for the physical design rules are changing from minimizing spacing and maximizing packing density, to minimizing noise and signal integrity problems. A design rule set that emphasizes minimum spacing doesn't necessarily help in today's environment of wide internal structures and large embedded blocks.

The physical size of a wide-bus structure is not determined by the metal pitch, but by the minimum spacing needed for contacts and vias (see Figure 1). A fully contacted metal pitch with aligned vias has spacing rules almost three times wider than just the minimum metal. The pitch is only about twice as large for staggered vias, but the staggering of the contacts causes longer lines than the aligned variation. The change to an increased metal pitch should help make the parts go faster by reducing the lateral and fringing capacitance on each line. The tradeoff will be that more of the lines will be longer, canceling the gains from the lower parasitics.

Trends and issues

ISD Magazine has been looking at the trends in ASIC technologies and has published a number of reports on the performance of the most current generation of semiconductor technologies. Although we started working on this topic two months ago, the number of variants in a single process created too much data for most of the ASIC vendors to summarize, with the result that we couldn't get enough responses to publish. The newest wafer processes - whether it is a 0.18-ým, 0.15-ým,0.13- ým, or even a 0.10-ým process - will have the features of faster, lower power per gate-MHz and much higher circuit density than anything else we have available today. The biggest issue, as always, is that with every process generation along come new problems that are a function of the smaller, faster, more complex production.

When the industry moved from 0.5 ým to 0.35 ým, the designers had to spend significant amounts of time and energy on correcting timing problems, in addition to addressing the area concerns. In the 0.18-ým generation, the additional problems include signal integrity, noise, power, metal migration and reliability, as well as thermal problems resulting from the increased internal device counts (see ýPredicticing Semiconductor Failure Modes, p. 64).

In the 100-nanometer ICs - two full semiconductor generations down the road - the device physics associated with the macro-level models we use for transistors may break. Potential problems for the year 2002 processes are hot-electron effects, charge tunneling, and designs becoming increasingly interconnect-limited. The number of layers of interconnect needs to increase up to eight, or as many as twelve layers to handle the number of connections on the IC. However, manufacturing may only be able to make six to seven layers by that time.

The high speeds and fast edges will make the inductive effects more important in the interconnect, while the total power will cause the ICs to run hot. But, more importantly, the thermal gradients will cause timing problems because the parasitic R's and C's will change at the same time that the transistors change operating parameters.

The semiconductor manufacturers have pushed the limits of photolithography for many years and the resulting ICs we have today have performance that is beyond the wildest dreams of the designers of a mere 10 to 15 years ago. Through all of the changes over those years, the industry has run up against many problems that, at the time, were considered to be insurmountable. Obviously, we have overcome the problems of those past eras and the expectation is that we will continue to advance the technology at a similar and rapid pace going forward.

Tets Maniwa has become the new Community Leader for EDA and site manager for the latest CMP website offering, EEdesign.com, chartered to provide a wealth of information and resources to the digital design community. Tets will continue to offer his insight and industry perspective on regular intervals here in ISD Magazine. In addition, look for his weekly commentary on the new website.

To voice an opinion on this or any other article in Integrated System Design, please e-mail your comments to mikem@isdmag.com.