Big things come in small packages, oft times, and it's no exception for programmable logic devices. In the past, PLDs and FPGAs have hovered in the tens, or at best, hundreds of thousands of gates and have been limited in their use by size and speed considerations. Today, however, these devices may include well over one million gates, and can offer a powerful addition to a design strategy that might previously have been conceived only as "strictly custom." Product developers are finding that, in having to deal with the daunting tasks surrounding design, PLDs can help them to retain crucial flexibility much longer and much farther into their process - clearly an intuitive and appealing idea.

It's not something that's right for everybody or everything, but in many cases it's just what the doctor ordered. Valerie Rachko, of Mentor Graphics Corp. (Wilsonville, OR), says that PLDs are "hitting the tornado and ramping up fast." She explains that "in the past, when you thought of PLDs, you thought of small devices. But now, with the type of devices coming from companies such as Xilinx (San Jose, CA) and Altera (San Jose, CA), they've become an option for many, many companies that would not have considered them in the past."

Not surprisingly, Cliff Tong, vice president of marketing at Altera Corp., agrees. According to Tong, designers are beginning to see big advantages to the PLD design strategy. He argues that the technology today has reached such a level of maturity that if product developers can use programmable logic, they will. The only factor holding them back is the technical feasibility of the approach. The question, he says, is no longer whether or not the programmable device is big enough; the question is, does it run at a high enough speed to meet the specifications and is there the necessary intellectual property (IP) available to facilitate the use of the PLD in the design.

To keep a perspective on the size of the market, both for the products and the tools, current estimates set this year's PLD market at a shade over $1 billion, while the market for the vendor-supplied tools that help support the effort hovers at around $60 million (a small, but feisty part of the overall EDA market, currently in the neighborhood of $3.2 billion). The PLD market is poised to grow, however, according to many industry watchers. There's simply too much worldwide demand for product, and too large a range of target applications, for the ASIC developers to handle it all.

Begin the beguine

As is the case across the EDA landscape, the format for design entry is up for grabs these days. (see "Focus Report: Design Entry and Core Encapsulation," ISD Magazine June 2000 p.92) The two basic options include text or schematic entry - or, more often than not, a combination of the two.

So, in the case of PLD products in particular, what are designers using to get their specs entered into the flow? Traditionally, PLD design has been a schematic-entry type of exercise because of the intuitive ease-of-use and control the technique offers. It's true that text (Verilog or VHDL) entry has been of growing importance over the past several years - and the tools have reflected that - but new design philosophies are strongly re-affirming the value of the schematic-entry school of thought.

According to Dave Greenfield, Altera's director of development tools marketing, it's easy to understand why. SOCs and other big chips are pouring out of the fabs at a steadily quickening pace. Many designers and product managers are beginning to feel that the only way to get the huge designs completed within the required time-to-market window, and with the necessary level of quality and yield, is to resort to partitioning the designs using a hierarchical approach.

This strategy allows a project to be divvied up across team members and across potentially diverse geographic locations. It's also a strategy which lends itself beautifully to schematic specification entry and documentation.

Various takes on the schematic representations can be used to provide different viewpoints with respect to a hierarchical design. For instance, top-level schematics can be used for evaluating architectural considerations on-chip, while block diagram representations can prove useful for the partitioning tasks.

Diving into the details

This is not to take away from the continuing value of text entry. Clearly, as Verilog and VHDL play a bigger and bigger role in the opening salvos of a PLD design, crucial portability across logic vendors is enhanced. The ease of documentation within the body of the code adds to the attractiveness of HDL for the designers - that, and the speed of interface to the synthesis phase of the design flow. This is particularly true in the hugely important area of IP reuse.

Code and documentation are pivotal for capturing the characteristics of a reuse block and for entering the block into a larger design under development. The size of the PLDs under development today is quickly approaching a level that will demand the use of IP in order to limit the "limitless" options of the programmable logic device.

Some would say that, graphical or text, it's not the entry choices which are complicating the process of PLD design - it's file management. Rachko says, for instance, that 50,000 to 100,000 files are a lot of data in "HDL land" and it's a tough task to keep track of it all. The designer's got to keep an eye on vectors, scripts, and numerous types of objects; the whole thing can be overwhelming without the right kind of structures in place to manage the data.

A number of the PLD tool offerings, therefore, incorporate standard features for various forms of data and project management. As mundane as this aspect of design and development may be, it's often and ultimately "in the details" where the elegance of a concept is translated into reality. It's appropriate to point out that, according to Don Davis of Actel (Sunnyvale, CA), the complexity of an ASIC design makes file and revisions control a huge problem. However, he says, FPGAs are generally smaller projects and they present a somewhat less problematic challenge in this aspect of the design.

Clearly IP reuse and "pre-fabricated" components are factoring into the efficiency of design and use for PLDs, just as in other realms of chip development. Davis says that "FPGAs are going into every type of application. An FPGA, from an IP standpoint, is starting to look like an ASIC. In fact, anything synthesizable is fair game."

Accordingly, the PLD vendors provide a range of libraries to their customers, which enhance and facilitate the use of their products. The PLD tool providers are, therefore, required to keep close tabs on the big vendors. And it's hard to ignore the fact that in today's market, Altera and Xilinx own the lion's share of the PLD business. As quickly as things change in the semiconductor industry, however, the two big players should be aware of their healthy competition aggressively exploring the market as well. The smaller players are not willingly acceding a joint ownership of first place to the 'big guys' and are busy utilizing all of the arsenal offered by today's PLD tool vendors to play a hearty game of catch the leader(s).

Multi-tasking

In addition, there's an overlap between the PLD vendors themselves and the vendors of the associated tools. Clearly, as companies develop an internal expertise to produce these products, they frequently end up, at the same time, developing tools that are useful for the process, along with effective and marketable design flows. They turn around and package the tools for commercial purposes, while keeping the commodity part of the business growing as well.

Meanwhile, although some say that the PLD tool flow is not as effectively integrated as the ASIC flow, there's a lot of work going on in this area today and, given the market pressure to move to more programmable device design solutions, the flows can only improve with time.

The PLD synthesis tools, for instance, have been improved and refined a great deal over the last several years. They are building off of their successes in the ASICs area, according to Jackie Patterson, director of marketing for FPGAs at Synopsys, Inc. (Mountain View, CA). She says that PLD design has been one of the later holdouts in the manual art of design in comparison to the more widely automated design styles associated with ASIC-type products. Subsequently, she argues that although there's been an "evolution" in creating PLD synthesis capabilities, there's been a "revolution" around the fact that the PLD design strategies are becoming almost as tool-intensive as their ASIC counterparts.

Clearly there's still an independent streak in the engineering population that maintains, "I can do it better myself." But, the counter-point comes from the pressure to meet product development deadlines, which in turn nudges logic designers towards a more automated, tool-use mentality.

As in many other tool categories within the EDA industry, folks continue to tweak and twiddle with the business model around PLD tools. Mentor's Rachko points out that the small, start-up design houses are very sensitive to the cost of tools, more so than the big players in chip development. Term-based licensing is a way to mitigate the cost of the PLD tools by helping to avoid the potentially large front-end costs of purchasing a tool seat outright.

It's a model that is quickly propagating throughout the EDA industry - partly as a move to service the small customers and partly as a nod to reality. Many vendors acknowledge that the tools evolve and change so quickly that their customers, big or small, are perhaps best served when they don't have to commit large financial resources to a wholly-owned version of a particular generation of software. Rachko says that the principle competition today to commercially marketed PLD tools and flows are those "jimmied up" by the customers themselves - all the more reason why smaller entry costs for the PLD tools help to increase the appeal to potential customers. If the vendors are going up against the (perceived) no cost/low cost options of in-house tools, the sales effort is definitely facilitated by the (perceived) low cost of the term-based licensing model.

Altera's Tong points out that the move to system-on-a-chip products is having an overwhelming impact on many aspects of the industry today. It's forcing a recognition of the need for big chips, very capable EDA tools, and lots of IP that's both accessible and useable. There are few in the business today that would take issue with him.

Synopsys' Patterson says the mantra about verification and timing closure - and the associated problems of accomplishing those ends - are as true for FPGAs as they are for ASICs, again exacerbated by the move to SOCs. She says that better modeling software and advancements in both acceleration and simulation technologies will be necessary to further the cause of validation in design.

Meanwhile, the complex move to IP reuse will ease the stress in the PLD world, just as it promises to do for ASIC side of things. If smaller portions of a design can be developed, characterized, validated, and commoditized - who will complain if as designs grow bigger, they also grow better at the same time?

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