Evolution, the more conservative approach, tweaks the existing algorithms to increase performance while moving to accommodate the growing use of partitioning and hierarchical design strategies. Revolution would require a completely different set of algorithms in software simulators to handle the circuit models-or diffeent strategies entirely that emerge out of the domain of hardware tools aimed at verification.

That's not to say that everyone is toeing the line and accepting that evolution should be the norm. The folks involved in the hardware acceleration, emulation, and verification enhancement markets are finding all sorts of clever and inventive ways to speed up, max out, and rethink the whole simulation picture (which is, in fact, a part of the overall verification picture). Here in the Fall of 2000, those folks seem to be in the minority, however. It's true that their proselytizing is generating a lot of interest in the newer, somewhat unproven (from a critical mass-market perspective) strategies, but don't look for a mass exodus away from the existing stable of HDL simulators anytime soon.

I can C clearly now

The first challenge in an HDL simulator discussion is to define the terms. An HDL simulator is a software tool that takes a model coded in a hardware definition language and simulates circuit behavior based on that model. Traditional wisdom defines the HDL as Verilog or VHDL. Traditional wisdom is, however, changing with the demands for system-level design.

Few vendors are impartial at this phase of the discussion because for some, the lines are blurring as C, C++, SystemC, and other higher-abstraction languages emerge as contenders in digital design. But this is only for some vendors, not all. In fact, there are many that don't yet accept the C family as a subset of the HDL clan. They argue that it's true that, while coding in C is easier for some due to its flexibility and widespread user base, currently the code is translated into Verilog or VHDL before the simulator ever sees it.

Synopsys has thrown its backing behind SystemC-a language construct intended to bridge the gap between the overly generous-hearted C/C++ languages and the overly narrow-minded HDLs. Farhad Hayat and James Cardwell are among the technical marketing folks at Synopsys. Their comments on SystemC are interesting:

"Synopsys is providing (the simulation tools) that the design teams want in an evolutionary manner.

True, some teams are using C/C++ and Synopsys is supporting them, but C/C++ is really just being used as a front-end parser bolted onto the model, which is later configured for consideration by the HDL simulator.

A complete overhaul of the HDLs is not what's needed. Hardware designers, ASIC designers in particular, know and trust the HDLs and the tools built around them.

To meet the growing language gap, high-level constructs will be added to the Verilog 2000 standard."

Running out of steam

Alternatively, Dave Park, vice president of marketing for C Level Design, Inc., says, "The performance of HDLs-Verilog and VHDL-are coming under pressure to provide greater performance." According to Park, these HDLs are nearing the end of their usefulness from a performance standpoint as the size of the designs dramatically increase. He says that the are two clear reasons why C is the solution to the HDL dilemma.

First of all, it's basically "free," so the economics argue for C. In addition, the structures in C are far more complex and, therefore, better suited to handle today's design challenges; the complex data types and pointers in C do not have corollaries in the HDLs, he says. The designers, therefore, have two options: They can buy expensive simulators and continue to "flail away" in HDL code or they can use C freeing themselves from the confines of Unix and allowing themselves the liberty of working on a PC. Park also argues that the numbers of C programmers in the world offers a tantalizing opportunity to tap on that resource, to "use software guys to do hardware." Clearly, then, there are two main schools of thought.

C-type languages, or other high-level semantic constructs, are moving to completely take-over the design space-a process that is inevitable, although not happening overnight.

C-type languages and their ilk are not replacing, only complementing, the language choices and design options available today.

When worlds collide

Mentor Graphic's Dennis Brophy is currently chairman of Accellera, an industry standards body introduced in March 2000 as merger of two previous standards bodies: Open Verilog International (OVI) and VHDL International (VI). The mission is to standardize the two mainline HDLs to meet the current needs in system design and design reuse. Brophy says that until recent years, "our heritage would dictate that we only talk about analog or mixed-signal or digital extensions to the base HDLs." In the past four years however, he says people have expanded beyond that thinking to realize "the full level of what a simulator can comprehend."

Brophy adds that only by crafting new languages or improving upon existing ones will marked, orders-of- magnitude improvements in simulation and design productivity emerge. Brophy says that there is actually a measurable drop in design starts worldwide because the demand is for bigger, more complex, system-on-a-chip (SOC) designs, which are in turn absorbing the manpower and limiting the bandwidth in the design community. These big system designs are forcing the software and hardware worlds to collide. He argues that only if a co-design strategy is crafted, will an implementation technology develop that allows SW/HW development to occur within the same semantic.

C languages might shoulder the burden, but "you're not going to take an entire generation of designers and change them into C-language guys overnight. A discontinuity in coding styles won't happen," he says.

Given the level of discourse currently underway, it seems prudent then to restrict the discussion here to where we stand today, to address the current crop of HDL simulators and how the people that make and support these tools hope to improve, not replace, their offerings going forward-the "augmentation" strategy.

Augmentational exploration

There are guidelines for that augmentation. What people are looking to do is to increase the speed of the simulation without compromising the quality in the process. Therefore, the amount of logic compression is tweaked up and down according to the amount of "resolution" required by the designer. The higher the resolution (resulting from minimizing the logic compression), the slower the speed of simulation-but the greater the accuracy of the simulation in comparison to the results that could be expected in testing or verifying that design in real-world silicon.

Conversely, the lower the resolution (resulting from maximizing logic compression), the higher the speed of the simulation, but the lower the accuracy of the simulation in comparison to that obtained from silicon rendering of the design.

John Lenyo, director of marketing at Model Technology (Mentor Graphics) says that making these types of gradual improvements in the existing simulation algorithms is what the market is looking for. "We believe there's still quite a bit of bandwidth in that path," he argues in explaining the strategy for improving the tools by trading off between minimizing the information "you keep around" while still maintaining accuracy. If you control the size of the model, the simulation will "fit into the workstation longer," according to Lenyo. But, he adds, "if you collapse it too much, you can't see into it."

Old ideas revisited

Besides balancing performance and speed, there are additional techniques available for augmenting current HDL simulator technology. The debate continues, for instance, over the value of cycle-based simulation versus event-driven simulation. Cycle-based strategies run the model at near-operational speeds, allowing the designer to observe the behavior of the circuit in something akin to real time. However, within a particular clock cycle, the information is harder to come by. So, although cycle-based simulation still gets the nod for offering an intuitively pleasing basis for simulators, the fact that timing profiles of the simulated design are not addressed in cycle-based strategies means that the lion's share of simulators are still based on event-driven algorithms. In fact, at one point several years ago, cycle-based simulation was dismissed outright by the industry as having been examined and rejected. Today, as the designs push the limits of the abilities of traditional simulation tools, cycle-based simulation strategies are beginning to be accorded respect once again.

Judgement call

If the technology behind the most commercially successful tools today is not revolutionary, then how does the customer distinguish between one vendor's offerings and the next? Mentor's Lenyo has no problem answering that question. He says the judgement list is long and easy to understand: price, language support, ease of use, platform support, mixed language environment, ease of debug, and the availability of batch mode versus interactive mode are all important considerations. The intelligent customer should examine all of these factors in choosing an HDL simulator from today's current offerings.

Addendum to the December Focus Tables.