Intellectual Property (IP) is often sought out as a timesaving measure to shorten the design cycles of today's increasingly integrated systems. However, IP can only act in that capacity if it can be quickly and easily evaluated. IP - especially that created outside of the company - is by definition more difficult to evaluate than one's own design and requires an evaluation process facilitated by both the vendor and the user. Correct functionality, performance, and device utilization in the target technology are only the beginning in a list of items that should be investigated by the potential user. The expertise of the IP provider and the level of support they provide are also important; users must consider ease of customization and integration, as well as availability of test benches. In the ideal case, users should also be able to freely evaluate the IP in their target technology before purchasing - an option that is available to users in varying degrees.

One factor that has fueled the increased IP adoption in the semiconductor industry is the evaluation process. Designers must carefully weigh factors such as ease of use, functionality, customization, performance, price, and support when they select IP. Four aspects of IP evaluation are examined here: evaluation risk, customization, hardware verification, and simulation model distribution.

Evaluation risk

Even though IP has gained popularity, many designers are still cautious about using it. This is especially true for first-time users. On its face, using IP carries the risk of depending upon a design created outside of the control of the user. It is ostensibly the IP vendor's job to convince the potential IP user, therefore, that the product will meet the user's needs. Though many IP vendors achieve this end by establishing reputations and relationships over a long period of time, this approach does not necessarily alleviate the concerns of first-time users.

In many existing IP evaluation flows the potential user must license the IP before integrating it into a design, which prevents the user from evaluating the resource usage or performance (simulated or otherwise) in their application. Add to this the variety of licensing conditions that differ from vendor to vendor, as well as the time and effort involved for any customization that must take place, and it becomes clear that evaluating IP can be quite a lengthy and inconvenient process, even for seasoned users.

Mitigate and minimize

In order to mitigate problems, IP vendors should minimize the risks taken on by their potential customers. A vendor can take a variety of steps to minimize risks to the users including supplying examples of previous successes or references along with providing resource utilization and performance estimates for various implementations of the target hardware. The ideal strategy provides potential IP users with an evaluation process that allows them to integrate the IP core into their overall design, and evaluate both its resource utilization and performance with few or no licensing conditions involved until the users are satisfied with the result.

Unfortunately, significant challenges stand in the way of providing such an evaluation. In practice this type of evaluation can only take place with the cooperation of both the silicon vendor and the EDA tool vendor. The silicon vendor must provide up-to-date specifications on hardware implementation and timing characteristics to the EDA vendor so that the user can implement the IP core in the overall design to determine resource utilization and simulated performance that accurately reflects the real implementation. For their part, the EDA vendors must provide a tool that allows an IP core to be placed or fitted into its ultimate hardware solution for the purpose of determining resource utilization and performance simulation. At the same time, the tool must not compromise the IP vendor's security by allowing the user to implement the final hardware solution without licensing the core.

Under existing design development flows for custom ICs, the barriers to providing a low-risk evaluation are very high since the flows cannot prevent users from implementing designs in hardware once they have received the netlists or source code for the IP cores.

Programmable logic design flows, however, do allow for this type of evaluation because of the tight integration between the silicon and EDA providers. In some programmable logic design development flows it is possible for potential IP users to instantiate IP cores into their designs and compile the designs for both utilization and simulated performance numbers before agreeing to license the core.

One example of this type of evaluation is provided by Altera's Opencore technology. Users can evaluate Altera IP cores prior to licensing, which allows them to compile and simulate designs as well as to verify the function's size and performance. This evaluation process provides first-hand functional and timing data along with other technical details that permit an informed decision on whether to license the IP core (see Figure 1).

IP customization

Two other important elements of a successful IP evaluation are flexibility and ease-of-use. Often, IP requires customization in order to meet the specific needs of a user's design. In many existing IP evaluation flows, the vendor works with the user to understand what customizations are necessary, then makes the necessary changes. Such a process allows the IP vendor to collect consultation fees for the customization and also to better understand the user's end application.

The downside is that this process can be very time consuming, especially if the user requires several customizations to accommodate the common occurrence of changing design specifications; and it can be quite costly for the user as well. In addition, performing customizations demands a lot of the vendor's resources, limiting the undertaking of other projects. One solution to this situation is to allow the users to perform customizations themselves via parameterizable IP cores. Vendors need to provide IP solutions that are highly parameterizable so users have the utmost flexibility in using the IP in their designs. Parameterization should be built into the function in such a manner that it puts the IP user, rather than the provider, in control. Parameterization also allows the vendor to offer their product to multiple users who require little assistance, thus allowing the vendor to pursue other business activities.

Altera also provides a technology that allows parameterization of IP cores using the company's Megawizard Plug-in, a technique that helps users to integrate IP cores into designs without the use of third-party tools. Significant flexibility is provided to the user in customizing IP without changing the design's source code. Users can integrate a parameterized IP core in any HDL or netlist file using any EDA tool (see Figure 2). Using the technology, users can parameterize functional features such as number of Taps, sample rate, filter type, interpolation, and decimation factor. Users can also customize the core functionality and modify the performance to create an optimal design, therefore keeping pace with changing system specifications without having to re-architect an algorithm or target a more expensive technology. By providing these types of tools, IP vendors help users minimize the amount of work required to implement IP in their designs.

Hardware verification

A precise and reliable design verification solution that also provides an effective debugging platform is an essential element of IP evaluation. In order to facilitate the evaluation process, IP vendors need to supply a variety of development and prototyping boards. These boards speed system design by allowing application software development to begin earlier in the design flow. Also, hardware designers can be made available to verify IP functionality quickly and effectively. A development platform provides designers with a cost-effective solution to hardware verification.

The integration of firmware and software applications with hardware has been the traditional bottleneck in complex system designs. A development board allows both software and firmware engineering to employ a proven hardware platform early in the design cycle.

Having access to a platform early in the design cycle facilitates software debugging and integration, which allows the software and hardware to evolve in parallel and enable a shorter verification cycle. Palmchip's Surfboard hardware development board (DT-8110) is an example of a platform that offers an innovative solution for the development of a system-on-a-programmable-chip (SOPC). The Surfboard, which consists of Altera's APEX EP20K400E PLD and ARM7TDMI processor, enables hardware engineers to develop SOPC designs prior to committing them to ASICs and enables software engineers to start running software for the purposes of debugging and integration.

Hardware testing speeds the design cycle by replacing weeks of software simulation time. For complex applications involving audio, video, or high-bandwidth Internet access devices, real-time operation and debugging are essential. For example, consider PLD Applications' PCI20K-PROD prototyping board, which is a 32-bit or 64-bit, 33-MHz or 66-MHz PCI development that can be reconfigured in-system. This board enables the user to quickly implement the design with the IP core and test it in real time on a hardware platform.

Simulation model distribution

Traditionally IP has been distributed as HDL sources. The end user could tweak the source code to a certain extent to best suit his design needs, then compile and simulate the IP and use it in his design. The IP developer's intellectual properties in this case have been protected by non-disclosure agreements. This setup works well for some parties, but it does not work for the actual IP developer who has to maintain at least two sources of IP - VHDL and Verilog. In spite of these limitations, this methodology is still the most common.

Another way to supply IP is by creating encrypted simulator-dependent libraries or models. However, by doing so, the IP provider has to maintain multiple sets of encrypted libraries - a very tedious responsibility.

This process, in addition to being time and resource consuming, may result in the need to compromise between different results that are obtained by running different simulators.

A third way to distribute IP is as a source-level encrypted HDL or as an encrypted netlist, which is prevalent in the PLD industry. This method works well for the IP vendor, but makes it impossible for the user to make any modifications. With parameterization and risk-free evaluation, however, the distribution of IP as an encrypted netlist is a win-win situation for both the vendors and the users. Flexibility and ease-of-use are just a couple of major advantages PLDs have over ASICs. In the ASIC world there is no easy way for users to evaluate IP unless they build the ASIC with the desired IP in it.

Some IP vendors have enhanced the distribution method by allowing users to create simulation models that can be used in any third party VHDL or Verilog simulation tool. This method gives users the flexibility to use the simulation tools of their choice. Innoveda's Visual IP software enables users to create simulation models that can be used in either a VHDL or Verilog simulation tool.

Consider the source

Starting with a source HDL design, the IP vendor imports code into the Visual IP software. Before generating a protected model, they prepare a set ofvectors to drive the IP model and define which internal signals are visible to the end user. Vendors then specify documentation for their customers to use in evaluating their IP cores: functional descriptions, descriptive rules about the operation of the interface, clocking requirements, functional specifications of all operating modes, timing diagrams, and sample simulation results. Visual IP then generates a secure model, which can be used either on its own or embedded in a user's design (see Figure 3).

The IP market is still in its infancy and has a long way to go. In order to accelerate the use of IP, vendors need to provide a user-friendly experience with solutions that put the user in control. Risk-free evaluation, easy customization, hardware verification, and IP simulation model distribution and protection are the key ingredients of a successful IP evaluation.

Tapan A. Mehta is a product marketing manager at Altera Corp. where he focuses on DSP and communications IP cores. He has written and presented numerous journal and conference papers in this area.

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