Last month, I shared a glimpse of the 1999 International Technology Roadmap for Semiconductors ("New ITRS Roadmap Portends Massive Design Changes Ahead," December, p. 48). In this column, I'll focus on the shock wave anticipated for the EDA industry a wave that will include substantive changes in tool interfaces, design methodologies, and verification techniques, though probably not in platform. As in last month's column, I will simplify things by zeroing in on the year 2003, with a decidedly ASIC emphasis (by 2003, the term "ASIC" will be synonymous with system on a chip).

While design productivity is already an important business barrier, it will become far more critical over the next several years. By year 2003, required productivity levels must increase over 300 percent! Though designs will virtually explode in complexity during this period, the roadmap doesn't predict appreciable changes to the design cycle.

One area highlighted in the roadmap is the increasingly critical role of standards in supporting flow and IP interoperability. Other industries, the PC industry for one, have greatly benefited from standards that enable new technology to take root and create new markets. It's a sign of maturity for an industry to recognize the greater value realized by sharing at one level, while differentiating themselves at another.

The roadmap predicts that design complexity management will rise to a top priority for design flows. The watch words for the next decade will be hierarchy, abstraction, and incremental design. EDA algorithms, tools, libraries, and interface formats need complete retooling to support incremental design requirements. Complexity will also greatly increase because a greater array of simultaneous views into the design must now be traded off and managed throughout the flow. EDA algorithms demand greater interaction among views as part of the automated flow, even while the designer requires separation of concerns to concentrate on one aspect at a time.

The ITRS roadmap recognizes data management as a growing concern and a part of the design complexity equation. This complexity not only results from the order of magnitude increase in design size, but also relates to the need for a greater number of incremental techniques. Furthermore, the tight interaction of multiple views creates concurrency in how data changes and flows through the tools. To sustain the bandwidth of information flow required between all of these tools, as well as to support incremental techniques, it's apparent that many ASCII formats must give way to APIs. Sure, procedural interfaces are more complicated than file formats, but then again so are the designs they must support.

Perhaps the biggest issue in this transition will be how to package EDA technology in the new environment.

Perhaps EDAC can lead an industry debate on this topic.

Back to the library

Until recently, libraries for EDA tools have been relatively static, simply providing strings, coefficients, and parameters to internal algorithms. Yet the cross-coupling of various silicon effects will place more sophisticated demands on libraries than in the past. Library data will soon require domain knowledge of the methods to act on that data, and participate in a complex decision process. The impact of this shift will affect how tools and libraries are packaged and distributed. Modeling technology will necessarily continue to mature and advance, since descriptive models need to better support the above-mentioned concept of "separation of concerns."

The need for a system-level methodology is a central tenet of the roadmap. The current plethora of design tools and proprietary extensions to software languages indicates how far we have to go to converge as an industry. It also signifies the critical importance of this transition to the entire electronics industry. Yet higher abstraction levels bring about a natural divergence into more application-specific priorities and terminology, as well as conflicting semantic interpretations of abstract concepts. One challenge for the EDA industry lies in how to reduce the burden of manual model creation unique to each abstraction level and each point in the accuracy/runtime tradeoff space. While the predicted clock rates and interconnect lengths for 2003 foreshadow ominous timing concerns, many design applications will see power optimization steal the show from timing as the most critical challenge. The increasing functional densities and clock rates will create tremendous thermal and power grid distribution headaches, but an even more common challenge may be the need to maintain battery life in portable applications.

Unquestionably, logic synthesis sits in the middle of a large transition to integrate physical concerns. However, a broader view may hint at even larger changes ahead. The requirements placed on EDA flows for year 2003 may force a split in synthesis. The up-front portion, which requires designer interaction and control, will be coupled with RTL floorplanning, which also requires designer interaction. Synthesis optimization, in contrast, requires not only detailed physical design knowledge, but must also make concurrent tradeoffs with other optimizers as part of a correct-by-construction layout process. In addition, the roadmap predicts more specialized synthesis algorithms, each of which is optimized for specific portions of a design (control-driven, data-driven, communication channels, messaging/protocols, data path, memory, BIST, analog). Tools will need additional algorithms to automate the splitting and stitching together of design fragments to be acted on by the specialized technologies. Finally, the system-level methodology will enable a greater emphasis on correctly generating and verifying design constraints for synthesis use.

Design environment

As EDA algorithms split, recombine, and generally adapt to the evolving requirements, the designer's interface will adapt as well. One interpretation is that RTL floorplanning (also known as design planning) will evolve to become the designer's primary "command and control center" the virtual design cockpit. This new environment could integrate both the logical and physical views of a design, since it combines initial RTL synthesis (minus technology optimization) with a graphical front end for automated block placement and global interconnect synthesis. Furthermore, designers could better interpret the subtle information buried within textual reports from estimation and analysis tools, if graphically visualized in this environment.

Static timing analysis must undergo significant changes to address the effects of crosstalk and SOI (silicon on insulator) processes. The dense, long interconnects toggling at over 1 GHz in 7 or 8 levels of metal can create timing variations as high as 300 to 400 percent. Then again, SOI creates its own challenges for timing tools. While the introduction of SOI processes will reduce capacitance to further improve performance, charges stored in floating wells can create a complicated "memory effect" for which timing calculations must account.

The overwhelming complexity of multi-rate systems, multi-voltage systems, and multi-temperature regions in silicon will add to the ever-expanding verification tool box. We will see an accelerated trend towards earlier and higher levels of abstraction and verification. However, even these developments won't satisfy the demands of detailed design verification, resulting in a new focus on incremental verification.

Given the sheer size of design data, the need for increased accuracy to represent silicon effects, and strong time-to-market pressures, we should consider more integration of statistical methods into everyday EDA tools. Certainly, analog circuit verification of even very small blocks at 70 nm could require days or weeks of simulation in high-accuracy mode. Instead, properly characterized statistical models might more efficiently identify potential design risks by analyzing specific criteria with known statistical patterns and correlation. At silicon processes below 100 nm, manufacturing fluctuations will be significant enough to command explicit handling in many libraries and even some commercial EDA tools.

The ITRS roadmap design chapter highlights the need for formal methods to play a greater role in validating designs of the future. While equivalence checking is commonplace today and model checking is still waiting to "cross the chasm," future solutions may need to consider hybrid techniques that blend multiple algorithms for improved scalability and overall usability. These methods aren't limited to the purely formal arena, but will also include blending with simulation techniques. Data-centric verifications may benefit from symbolic simulation, while designers can extend the power of block-level model checking using theorem proving at the block interfaces. Formal techniques may also offer promise in the automated generation of assertions and properties, or in the generation of abstraction functional models for simulation.

Given that the roadmap predicts built-in self-test (BIST) to account for 30 percent of all IC testing in 2003, integrated design-for-test strategies will become essential to meeting cycle time needs. EDA tools that can automatically architect and synthesize all self-test logic are sorely needed. The roadmap also indicates that the reverse technique may also grow as a significant technique to manage the testing problem, particularly for analog, RF, or other alternative technologies.

EDA tools of the next five years will undoubtedly require lots of memory, 64-bit addressing, native multithreaded algorithms, and better utilization of workstation clusters. In my opinion, the continuing needs for tremendous scalability, reliability, and repeatable process encapsulations in batch scripts don't appear to favor any substantial shift towards Windows NT platforms. In fact, the recent surge in popularity of Linux around the world, and in particular among EDA suppliers, will likely further cement Unix as the high-end platform of choice.

What new EDA technologies can we expect over the next five years? Without question, inductance-aware timing, power, and signal-integrity tools will become standard practice in front-to-back design flows. I suspect we will see various experiments in dynamic logic synthesis and analysis, though I anticipate that these will be short-lived. As copper and low-k dielectrics compete with cost and yield, mixed metallization (copper/aluminum) may require occasional new variants of familiar tools. Finally, RF EDA technologies should begin to better integrate libraries, interfaces, and analysis results into the traditional flow. I encourage you to visit www.itrs.net for an online edition of the roadmap. I also welcome your feedback, which I will include in future columns to help establish an open industry debate.

Contributing editor Steve Schulz is a senior member of the technical staff in Texas Instruments, Inc.'s Worldwide ASIC division in Dallas. He serves on the board of directors of VHDL International and is the executive sponsor of the System-Level Design Language.