Here we describe the use of a commercially available tool to help measure current test coverage and identify blocks of low test coverage for pattern enhancement while in the register transfer level (RTL) design phase. The tool inserts zero-delay buffers into the RTL design that can then be fault graded. Correlation results that have gate-level single stuck-at fault (SSAF) grading reflect the advantages of performing fault analysis in the RTL design phase.

Traditional fault grading methodology

Gate-level test grading is becoming increasingly difficult to fit into today's design cycle. Circuit density continues to increase, as seen in Motorola's latest embedded microcontroller, the MPC555. This microcontroller contains a PowerPC core, 448K bytes of Flash, and 32K of SRAM, and 15 additional modules. Test efforts for such designs must be squeezed to fit into much shorter design cycles. For test grading to be a viable option in today's design environment, it must be done earlier than traditionally required in the past. Several aspects of gate-level fault grading are described here which provide motivation to seek out better solutions.

Requirements for test grading are an extension of a design's logic simulation environment in which the model is logic simulated using functional verification patterns. In addition, fault simulation requires the availability of tester out-put strobe timing information. Minimal tool requirements include the availability of compatible logic and fault simulators and an adequate number of workstations configured with suitable RAM to handle SSAF grading of the design netlist. If these areas are not considered, the results could prove unacceptable.

Figure 1 - Comparing timelines

RTL Grading appears much earlier in the design flow timeline than gate-level grading.

Fault analysis of synthesis-generated logic can prove difficult. Tracing logic functionality of the resulting gate-level logic is complex due to logic reduction, circuit optimization, and the way that the synthesis tool places and connects gate-level components in the schematic.

Synthesized design and test grade flow

The test grade flow is made up of fault simulation and fault analysis phases (see Figure 1). During the fault simulation phase, all patterns intended for production are fault simulated against an instantiated list of faults obtained by the fault simulation tool. The remaining undetected list is then used during the fault analysis phase for writing additional test patterns and for identification and removal of logically redundant or untestable logic.

To perform fault analysis to identify add-on vectors (AOVs) to be written, global analysis is first performed to identify hierarchical blocks with low coverage. Untested functions and blocks of untestable logic can be identified by analysis of low coverage sections. Clusters of related faults (multi-instances, parallel bits, etc.) are then analyzed. Once add-on patterns are generated and logically undetectable faults (LUDs) are removed from these areas, overall fault coverage should be recalculated. If fault coverage is still not adequate, single faults must be analyzed on an individual basis and additional patterns written. This can be costly in terms of staffing requirements if a deadline must be met, since the disposition rate is much slower than for previous stages.

An RTL grading approach

As mentioned, design cycles continue to be compressed with improvements in design automation. Fault simulation and add-on pattern generation cannot be started until a gate-level netlist is available. Since the current trends move netlist availability out later into the design flow, the time remaining prior to mask shop tape-out may be insufficient for completing fault simulation and add-on pattern generation on schedule.

Fault grading of inserted buffer faults at the RTL can begin as functional patterns become available, and need not wait on a gate netlist. Test coverage of the functional verification suite at mask shop is an important milestone, which can be used to give a sense of the overall test coverage quality when a spec annotation methodology provides the pattern generation. The resulting coverage and fault analysis information, obtained from test grading, can then be used for test pattern enhancement. This information can also improve testability features in specific areas if time is available to do so prior to gate-level netlisting.

Buffer insertion is the most critical part of this RTL grading process, an approach based on work done by Mao and Gulati. The core of the process modifies the original RTL models by adding zero delay buffers at the proper locations within the models. Buffers are added between variables and executable statements in the RTL model; stuck-at faults are then injected at the input of those inserted buffers to model RTL variable stuck-at faults. After buffer insertion has been successfully completed, any commercial fault grading tool which handles mixed gate and RTL can be incorporated to perform standard single stuck-at fault grading, and to report fault coverage.

The suggested RTL grading flow can be achieved using the TurboFCE tool to perform the RTL buffer insertion; the Verifault tool performs fault grading (see Figure 2). The required inputs include the Verilog RTL model as well as the functional or add-on test patterns. Outputs include the fault grade reports, an undetected fault list, and an intermediate hybrid RTL model (which could be used to assist in low coverage analysis). The major areas for test improvement found in the RTL grading flow are test pattern enhancement, and RTL model testability enhancement.

Figure 2 - Buffer insertion

The RTL grading flow improves with the insertion of buffer methodology.

The test pattern enhancement process is triggered by fault analysis of low-coverage blocks. Pattern enhancement can be accomplished either by modifying existing test patterns or by writing new add-on patterns. RTL model enhancement usually takes place in the early stages of the design cycle where parallel development of models and test vectors could benefit each other.

Advantages of RTL fault grading

Although the test grade functions are similar to gate-level grading, grading at the RTL seems promising in attempting to meet grading time constraints of the design cycle. Since the level of abstraction is higher than gate level, the total fault population and resulting undetected faults are proportionately smaller, reducing required engineering resources. Also, the rate at which fault analysis can be completed should be faster than analysis of the more difficult gate-level faults coming from a synthesized gate-level netlist.

We tested six design modules, most of which appear in the MPC500 family: bus interface modules, a counter module, Flash memory periphery, Flash control, and a 64-entry queued A/D converter. These elements are common in today's modular design environment. Available test patterns varied from 4 to 27 for individual modules. Sizes of design modules also varied from 0.2 MB (MPC590 CNTC Module) to 0.6 MB (Flash control module). Both optimistic and pessimistic buffer insertion modes were utilized for each of the RTL modules. Each buffer insertion mode produces a different instrumented Verilog RTL module. Both optimistic and pessimistic buffer-inserted design modules were fault simulated for comparison with gate-level fault simulation results (see Table).

Who's fault is it anyway?

Analysis of the undetected fault list of a buffer-inserted RTL model parallels gate-level fault analysis. Cluster faults (parallel instantiated structures) along with individual faults, exist at the RTL as they do in gate level.

An RTL control signal path that is laden with undetected faults can indicate untested functionality much as it does at the gate level. Tracing the probable cause of why an undetected node remains (after fault simulation of all available patterns) can lead to identification of add-on patterns that need to be written. The reason could be due to some basic functionality that was missed in the pattern verification methodology or a more obscure boundary condition represented by the undetected fault. Untestable nodes due to unused or redundant logic will also remain as undetected faults until identified, similar to procedures in gate-level fault analysis.

Assessment of correlation results

Our data indicates that fault coverage of buffer-inserted RTL models are within 0.6percent to 13percent deviation from their gate-level counterpart. Continued tool enhancements allow a further closing of the coverage gap. The topology of an optimistic RTL model makes grading of its inserted buffers similar to grading of gate-level node faults. The topology of a pessimistic RTL model makes grading of its inserted buffers similar to grading of gate-level input faults. As we expected, the sum of the fault populations of the optimistic and pessimistic model of a specific design module was usually less than its gate-level fault population. The difference seemed to be contributed by other gate-level faults such as output faults.

In our study, the fault population of most optimistic models ranged from 1/4 to 1/2 of the gate-level fault population, while for pessimistic models it ranged from 1/3 to 2/3 of the gate-level population. This observation may help to refine the buffer insertion process in the future for better correlation between RTL and the gate-level fault list. The resultof this refinement would provide accurate identification of low-coverage blocks as well as to improve overall coverage estimation.

Tool limitations and trade-offs

As mentioned above, there is one critical fault grading limitation that crops up during use of the fault insertion tool. Adding buffers for order-dependent statements (e.g. blocking assignments in terms of Verilog) may alter the functionality of the original RTL model. Since the register transfer logic is at a higher level of abstraction than gate level, some loss of accuracy will therefore result from a fault grade method based on RTL. If grading to 100percent gate-level SSAF coverage is required, the tool may lead to more easily identified add-on patterns, redundant, and untestable logic, but can't replace the gate-level fault analysis completely. Gate-level fault simulation of all patterns (including RTL add-on patterns) needs to be completed, followed by processing of the remaining undetected fault list, this is a process normally associated with gate-level test grading.

RTL grading can help to assess the approximate gate-level test coverage prior to the gate netlist being available. The availability of RTL fault grade results early on in the design cycle can help to support the add-on vector generation effort for obtaining specific SSAF coverage level prior to mask shop entry. In the continuous effort to improve design verification, testability design, and manufacturing test development, new tools and techniques have been explored.

There are a number of RTL code coverage tools available in the market. In general, these tools check for executable statements, branch conditions, expressions, and possible paths in a sequential block that have not been exercised during testing. Code toggle information is also available from specific tools. Although the tools don't provide direct testability analysis information and don't guarantee complete functional testing, some have been used to measure and enhance RTL code coverage.

The need for efficient RTL testability analysis tools is obvious. Such tools would help to identify poor controllability or observability of behavioral structures. These tools would also suggest early design measures to improve testability of the design so as to reduce the complexity of testing. Employing such information should result in better fault coverage through structural and/or functional testing.

RTL SSAF grading

We chose this strategy to meet realistic functional verification goals while continuing to reuse the functional test suite for manufacturing test. Test grading of single stuck-at faults at the gate-level has been employed to achieve a minimum of 85 percent of the test coverage goal prior to mask shop-an empirical goal based on past product history, which has indicated good functional coverage. Because of the satisfactory correlation results obtained in this study, buffer-inserted RTL grading can be employed as a replacement for gate-level grading in achieving pre-mask shop entry test coverage goals. To minimize the effects of the environment and simulation tools on correlation, the same fault simulator and strobe timings should be used as are currently employed for gate-level simulation.

An increase in RTL coverage will likely result in a corresponding improvement of fault coverage at gate level as well. Early RTL grading will allow opportunities for identifying redundant logic, potential design modifications to enhance testability and generation of add-on patterns to improve gate-level test coverage.

One final word

Today's short development cycles and large, complex designs create a challenging environment for gate-level test grading. The buffer insertion tool has made SSAF grading at RTL a second alternative to the gate-level grading technique. TurboFCE was developed to meet this need. Six designs modules have been used in this study and the results showed a 0.6 percent to 13 percent correlation between RTL grading and gate-level grading. A similair issue in need of a solution involve tools capability for handing buffer insertion to the blocking statement areas.

Further research is also needed to fully understand correlation behavior between this RTL grading technique and gate-level grading-and how to effectively assess this tool's use for fault analysis and AOV generation. Recent techniques and tools have allowed rapid design, DFT, and ATPG at the RTL. Therefore, an effective use of multiple tools at RTL promises a possible reduction in development cycle time.

Eric Hoang is a design for manufacturer manager in the advanced vehicle systems division of Motorola, Austin, TX. He previously worked for Texas Instruments.

Jamie Fontenot is a design for manufacturer manager in the advanced vehicle systems division of Motorola, Austin, TX. He previously worked for Texas Instruments.

Kuang-Hsien Chen is a design for manufacturer manager in the advanced vehicle systems division of Motorola, Austin, TX. He previously worked as a LAN development engineer at IBM.

We would like to acknowledge the contributions of Augusli Kifli and Laung-Terng Wang of Syntest Technologies, Sunnyvale, CA, in preparing this article.

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