Library-management tool The PCB Librarian Expert is a library management tool that supports consistent source-data from which to derive electronic design automation (EDA) library parts. The tool software enables library creation and management by using source-level data standards based on the extensible markup language (XML). The library-management tool supports library-data generation for use by printed circuit board (PCB) designers and engineers with the latest versions of Cadence Concept HDL schematic and/or Orcad Capture CIS schematic with Cadence Allegro layout software as the backend layout tool. The tool's software also supports the datasheet XML standard for pin and package definitions from the electronic component information exchange (ECIX) project's ECIX Quickdata Specificationsýthese are dedicated to designing standards for the creation, exchange, and use of electronic component information. The tool also incorporates built-in data management capabilities that enable the user to control access to the library data for modification and then populate reference libraries from a data vault. PCB Librarian Expert is available this summer and is priced at $35,000. It will be available on Windows NT and UNIX operating systems. Cadence Design Systems, Inc. San Jose, CA. Contact www.cadence.com

Noise tool Gatescope is a new class of signoff tool for large, cell-based ICs that enables designers to perform noise analysis to ensure electrical integrity of their designs before tape-out. The tool employs assertion-based technology to identify and correct noise problems caused by cross-coupling effects in ASIC designs at 0.18 ým and below. In high-complexity deep-submicron ICs, cross coupling between narrow-pitched metal wires on multiple layers creates the unwanted migration of electrical signals between wires or through substrate materials. Designers can analyze the impact of noise on both functionality and delay. Using a deterministic, transient-analysis technique, the tool performs methodical elimination of false errors on multi-million gate designs, so designers can focus on true noise problems. Additionally, an in-place optimization feature for automatic repair of noise failures generates ECO netlists for incremental place and route that results in a reliable IC. Gatescope is now available for Unix, Sun Solaris, and Linux. Standard pricing starts at $75,000. Moscape Inc. San Jose, CA. Contact www.moscape.com

Schematic-based tool Schematic Logic Probe (SLP) is a software realization of traditional tools used for debug, such as paper schematics and physical probes. SLP allows design engineers to control and observe electronic system operation via a software configurable schematic of the system's design and a standard IEEE 1149.1 interface. Systems are growing complex due to higher levels of integration. Use of fine-pitch SMT and large pin count BGA packages has reduced accessibility in the system. SLP addresses various concerns related to design complexity and dramatic increases in debug time. SLP provides a method for full access to the system's logic as well as a method to cross-reference that logic operation to a display of the system schematic. The SLP GUI displays a schematic of the Unit Under Debug (UUD) annotated with observed logic values from device pins. Users can search for devices, nets and traverse off-page net references without sorting through pages of paper schematics. The tool tackles the complexity problem by enabling engineers to select specific portions of the design that they want to debug, combining logic from multiple pages of the schematic into a single view for debug, the company said.

Engineers can begin 'probeless' debug for $1,995.00. SLP is available now for $1,995 and, additionally, a full working 30-day trial version can be downloaded from the company's web site, www.intellitech.com. Intellitech Inc., Durham, NH. Contact www.intellitech.com.

Equivalence checker Formalpro equivalence checker offers an advanced debug environment and claims to do a complete verification of million-gate designs in minutes. Formalpro uses an algorithmic-based approach, capable of reading VHDL and Verilog designs at the RTL and gate level, to prove functional equivalence between two designs throughout the entire design flow. The tool automates the verification process by performing matching, solving, and debugging to give users the essential process improvements. Formalpro is currently available and is offered at U.S. list price of $110,000. Mentor Graphics Corp. Wilsonville, OR. Contact www.mentor.com.

RISC Core The LX4189 is a 32-bit RISC core optimized for 0.15-ým silicon processes. The LX4189 is especially targeted at communications applications where performance in the most advanced process is critical. At the heart of the LX4189 is a new central processing unit (CPU) with a 6-stage pipeline. The newly-added pipeline stage is dedicated to instruction-memory access. This allows the LX4189 to access more memory, while keeping the clock frequency high for high throughput. At 0.15 ým, the LX4189 can push the clock speed to 266 MHz (worst case process, industrial temperature) without using full-custom circuit designs, according to the company. The core will deliver the 266 MHz clock speed with just one mm2 of die area in 0.15-ým silicon process. In addition, it also comes with an optional high performance multiply accumulate unit (MAC) for DSP related applications. The LX4189 is designed specifically for packet processing, voice over IP, and DSL modem applications, where clock speed is critical for the wire-speed throughput of the system. The Lexra LX4189 is available now for a single project license fee for RTL of $350,000. Lexra, Inc. San Jose, CA. Contact www.lexra.com

Open-source library enhancements Synopsys' new Technology Access Program (TAP-in) open-source feature will initially make available the Liberty library and Synopsys Design Constraints (SDC) formats. Syntax checkers for these formats will also be included as reference implementations. The open source licenses for Synopsys Liberty and SDC are free and available now through the TAP-in program. Additionally, the on-line (www.synopsys.com) click through license will be available with the syntax checkers following. Current TAP-in licensees can upgrade to open source at their convenience. Liberty currently is supported by more than 60 semiconductor vendors with more than 400 submicron libraries. Synopsys Inc., Mountain View, CA. Contact www.synopsys.com

Verilog and VHDL Design Checker Nlint is a new design rule checker for Verilog and VHDL. The tool is integrated with Novas' Debussy knowledge-based debugging system. Nlint helps designers create syntactically and semantically correct HDL code by performing source code checks to ensure conformance with design rules such as synchronous design, clocking scheme, and naming conventions and testability. Nlint works stand-alone as well as with Debussy. The product is available from Novas and on the Toolwire Design Chain Management (DCM) Network. Toolwire is an application service provider offering web-based pay-per-use access to EDA tools and services. Through Toolwire, Verilog and VHDL designers have access to Nlint anytime or anywhere through their web browser. Nlint for Verilog is available now for Unix, Linux, and Windows NT platforms. Nlint for VHDL ships in Q4. Pricing is $14,900 for a floating local-area network license. Pay-per-use pricing on the Toolwire DCM Network starts at $9.50 per run. Novas Software Inc. San Jose, CA. Contact www.novas.com

Physical implementation suite Teraplace is a physical implementation tool suite developed for issues of timing closure and deep submicron (DSM) interconnect delay. Extending traditional placement to include virtual routing, extraction with delay calculation, timing analysis and optimization, the tool suite is comprised of Teraplace, for timing-driven placement and two plug-in optionsýTeraoptimize, for physical optimization and Teracts, for clock-tree synthesis. Central to its purpose is the tool's ability to balance multiple design constraints such as timing, routability, area, wire length, and signal integrity in an integrated environment built around incremental execution. Teraplace uses Terasearch, an adaptive placement algorithm, to balance multiple design objectives including timing, routability, and signal integrity. Teraplace then verifies final placement with a virtual router that replaces inaccurate assumptions and estimations of wire-load models with accurate parasitic data. Completing this process before detail routing represents the physical designer's best chance to optimize a design and avoid costly design iterations during the physical implementation phase. Teraoptimize addresses changes that occur during optimization by supporting incremental design changes that can have a major impact on routability. The tool's performance-based incremental placement (PIP) algorithm enhances standard placement by performing incremental placement that considers timing and signal integrity during physical optimization. Teracts focuses on solving the complexity of DSM clock structures. Leveraging accurate resistance-capacitance (RC) data and a built-in timing analysis tool, clock trees are synthesized to minimize clock skew. This is all done with information provided from the Teraplace placement system. The Teraplace tool suite is available now and runs on the Unix operation system including Solaris and HP-UX. Pricing starts at $50,000. Mentor Graphics Corp. Wilsonville, OR. Contact www.mentor.com

Web-based Design Service Picasso Op-Amp Optimizer, accessed through a standard web browser, automatically generates an optimized netlist from user-defined specifications for more than 50 types of op-amps covering a wide range of performance parameters and foundry processes. Designers log on to the Barcelona web site to gain access to the service. The user sets up the problem, and then initiates the synthesis and optimization runs. The Picasso Op-Amp Optimizer reads the specifications and provides the user with real-time feedback on possible design improvements and indicates which specifications may need to be relaxed to best meet overall design objectives. The system's tradeoff feature allows users to sweep constraints for a given objective. Once registered, engineers can design and simulate a circuit for free. Only when they are satisfied with their design and request a netlist are users charged. Pricing for the Picasso Op-Amp Optimizer will be based on the complexity of the circuit being designed, and range from $500 - $2000 per retrieved netlist. Process technologies ranging from 0.5 to 0.18 microns from TSMC, Chartered Semiconductor, AMI, and UMC will be offered for the op-amp service. Barcelona Design, Inc. Mountain View, CA. Contact www.barcelonadesign.com

DSP developer's kit The Motorola DSP developer's kit allows engineers to design and test DSP algorithms for the Motorola 56300 and 56600 families of DSPs. Integrated with The Mathworks Simulink and Matlab environments, the Motorola DSP developer's kit provides system-level and instruction-level co-simulation. The Motorola DSP developer's kit is a co-simulation tool for engineers who design algorithms for Motorola's 56300 and 56600 families of fixed-point DSPs, used in wireless handsets and base stations, multimedia, speech processing and audio devices. Specifically, the developer's kit offers a way to verify the behavior of assembly language routines for the 56300 and 56600 families of DSPs by inserting them into a Simulink model or Matlab program. The kit also contains built-in assembly code routines and an API that guides developers through the design process and allows developers to integrate their routines, the company said. Additionally, the Motorola instruction set simulator/debugger ships with the Motorola DSP developer's kit, allowing users to derive specific information about algorithm performance from their simulators. The DSP Developer's Kit is currently available for use on PCs running Windows 95, 98, NT and the Solaris platforms. Pricing starts at $600 for a single PC-based user. Mathworks Inc. Natick, MA. Contact www.mathworks.com