• FPGA design suite Innovate FPGA is a design environment for high-density field programmable gate arrays (FPGAs). The tool suite helps designers develop large-scale FPGAs through the combination of graphical hardware description language (HDL) entry, logic synthesis and verification tools. The tool suite integrates Visual HDL, Intelliflow, and Fusion tools with FPGA synthesis tools. Visual HDL enables designers to graphically capture finite state machines, block diagrams, truth tables, and flowcharts, rather than manually coding them in VHDL or Verilog. It simplifies and accelerates HDL-based design by automatically generating optimized HDL code for leading logic synthesis tools. A new feature of the tool is the ability to quickly go from graphics into FPGA implementation flows by launching the Intelliflow flow manager. Intelliflow unifies functional simulation, synthesis, place and route, and verification under a single user interface, regardless of target vendor or family. For simulation and verification, Intelliflow uses Fusion to functionally simulate the VHDL or Verilog generated by Visual HDL and verify the FPGA's timing and functionality after place and route. Intelliflow automatically passes the code provided by Visual HDL into synthesis for analysis, elaboration, and optimization. Once synthesis is completed, Intelliflow runs the FPGA vendor-provided place-and-route software on the synthesized netlist and then generates a PCB symbol for instantiation onto a board-level schematic. The list price for Innovate FPGA, including Visual HDL, Intelliflow, Fusion, and FPGA Express starts at U.S. $15,000 and is available immediately for the PC platform. Innoveda, Inc. Marlboro, MA. Contact www.innoveda.com
• Integrated Development Tools The Codewarrior for 68K/Coldfire provides compiler and debugger support for the entire Motorola 68xxx family and for Coldfire MCF5206e and MCF5307. The compiler provides significant performance improvements for optimized code generation. The debugger includes enhanced support for the Motorola PPSM (Personal Portable Systems Manager) library (version 3.2) and a new user-configurable register view that allows users to browse registers in detail. Codewarrior supplies a development option including an editor, compilers, linker, and debugger all within a single integrated development environment. It's supported by three real-time operating systems: Accelerated Technology Incorporated (ATI), Nucleus PLUS kernel for 68K, and Coldfire MCF5206e and MCF5307; Dr. Kaneff Engineering Consultants EUROS for 68K; and Motorola Hong Kong PPSM version 3.2 support for the Dragonball family of 68K processors. Codewarrior for 68K/ColdFire, Version 2.0, is available for Microsoft Windows hosts and is priced at $2500. Metrowerks, Inc. Austin, TX. Contact www.metrowerks.com
• Physical design system Dolphin Version 1.2 is targeted specifically toward customers designing with technologies at 0.18 ým and below. This version of Dolphin is able to calculate the path delays induced by crosstalk interactions on interconnects that are in close proximity on a chip. The system aims to meet the new manufacturing design rules such as end-of-line, fat-wire connections, minimum metal area, variable spacing based on width, and metal via antennae rules, at 0.18 micron. With the system, these new rules are built into the global optimization function and the layouts produced are ready for manufacturing without any modification. The new timing analysis technology allows it to analyze multiple aggressors for a victim net and produce an accurate timing result for the best and worst case timing paths. The tool optimizes for all design constraints simultaneously. It includes implementation for advanced deep submicron rules and calculates timing with signal integrity effects due to crosstalk so that it can achieve optimization without iterations after routing. It has improvements in clock tree synthesis and logic optimization as well as compatibility with additional third party tools through standards such as SDF, SPEF and, GDS II. Dolphin 1.2 is available immediately and listed starting at $420,000 for a single CPU perpetual license in the U.S. Monterey Design Systems, Inc. Sunnyvale, CA. Contact www.montereydesign.com
• Website for removing noise in SOC designs Noisecorrect.com is set up to provide electronic chip and system designers a way to avoid and correct noise in their semi-custom designs using the web. The site gives designers access to tutorials as well as services and software that help eliminate noise from designs. The site has noise-related design content in the form of examples and white papers, as well as noise specific references from published works. It supports a chat room where users can post comments, recommendations, references, and advice. A set of examples on the site shows noise tools can be used while on the site, as part of a consulting contract or by the designer offline. The examples act as tutorials that highlight the noise analysis operations and explain steps in the flow. The site offers a Java-based workflow demo that gives the designers a quick tutorial on how noise is detected and eliminated from submicron designs. Designers can upload design blocks, construct a workflow, run noise analysis software, and get results. The site provides immediate access to software for noise detection and correction. The software features include distinct-net Miller capacitances based on temporal interactions, multiple aggressor interactions on critical path victim nets, clock switching impact on surrounding nets, and a host of net isolation algorithms to manage the complexity of the large victim-aggressor datasets in multi-million gate designs. From the website, it's possible to initiate a special service offered to customers so that an entire cell-based design is analyzed block-by-block or full-to-correct for noise. Special arrangements are made for securing customer data and the customer is able to reuse the workflows to repeat the process, if desired. Workflows can be downloaded along with software so it can be run locally. Small, sample customer jobs under 10,000 placeable instances or under 40,000 gates can be run free of charge as part of a promotional program. Sapphire Design Automation, Inc. Santa Clara, CA. Contact www.sdai.com
• Semi-formal verification tool O-In Search is a commercial EDA tool using semi-formal verification technology to discover corner-case bugs in complex SOC designs. The tool works with the O-In Check design instrumentation tool and the Checkerware library of verification IP, which were released in March 2000. These products constitute a white-box verification system that uses knowledge of a design's internal structure to provide functional verification. Semi-formal verification combines simulation with formal technology in order to deliver the advantages of formal verification. Formal techniques target properties, or statements of design intent, and try to prove or disprove them. The users specifies these properties using checkers embedded as comments within their Verilog RTL code. The checkers may be drawn from the Checkerware library or specified using Verilog expressions. No special language is needed. Search must consider only legal stimulus sequences, since a checker firing due to illegal inputs is not a bug. No special constraint language is required to describe legal stimulus: The tool uses the checkers already on interfaces in simulation. Therefore, an engineer can be running Search on a design in a few hours. The use of checkers that have been verified in simulation means that the constraints will be neither too loose (resulting in illegal sequences) nor too tight (resulting in limited exploration of the design). By starting with a seed from an existing test, the tool supplements traditional simulation methodology and tool flow. All steps of Search, including seed capture and conversion of interface checkers to constraints, can be automated and incorporated into an existing EDA tool flow. When the tool discovers a new way to fire a checker, it reproduces the stimulus sequences in a standard Verilog simulator. The current production release of O-In Search is the first to the general market. The North American list price is $100,000. O-In Design Automation Boxborough, MA. Contact www.O-in.com
• Power analysis tool Primepower is a full-chip power analysis tool for complex multimillion-gate ASICs. The tool allows the users to verify that their IC designs meet power budgets and specifications, select the proper packaging, determine cooling requirements, and estimate the battery life for portable applications. Primepower is an integral component of the Synopsys power-management methodology that includes Power Compiler for optimization and Powerarc for library characterization. The tool enables designers to estimate the power consumption of their ICs well before they hand off their final netlist to ASIC vendors. For ASIC flows, the tool features accuracy, performance, and capacity together with the details of power dissipation in the design for every simulation event. The tool works with Verilog and VHDL simulators, Verilog-XL, and Modelsim. Primepower is currently shipping and per-copy pricing starts at $78,000. Synopsys, Inc. Mountain View, CA. Contact www.synopsys.com
• Synthesis tool Leonardo Spectrum 2000 with Timecloser technology is a synthesis tool that enables timing optimization based on accurate, physical data for field programmable gate array (FPGA) design. The tool also incorporates a new Xilinx floorplanner interface and new bi-directional place and route interfaces for Actel, Altera, and Xilinx program-mable devices. The new interfaces are designed to enable the tool to read physical place and route data. The tool identifies critical paths by combining placement data and optimization algorithms, reducing the number of iterations. The tool combines restructuring, clustering and placement algorithms. Leonardo Spectrum 2000 is available immediately. The Timecloser technology is available in the Level 3 version of the product. U.S. list price starts at $17,500. The tool runs on Windows NT, 95, 98 and 2000, Solaris and HP-UX platforms. Exemplar Logic, Inc. San Jose, CA. Contact www.exemplar.com
• IP Internet distribution security tool IP Gear version 1.1 enables secure international distribution of semiconductor intellectual property (SIP) over the Internet. The new version of IP Gear adds security and control features to enable system houses, ASIC vendors, and third-party library and SIP suppliers to connect customers and suppliers in a protected manner. It also has enhancements for building and managing an enterprise SIP repository. The tool includes five new features: component access control, international language support, multiple component and deliverable download, classification-sensitive editing and viewing. IP Gear 1.1 is available now. Pricing starts at $150,000. IP Gear server software runs on Solaris and HPUX and all that is needed on the client side is a recent Netscape or Internet Explorer browser. Synchronicity Marlboro, MA. Contact www.synchronicity.com
• Transistor-level simulator Accelerated transistor-level simulator (ATS) 3.0 allows Cadence analog design environment users access to simulation and verification of mixed-signal designs. Its features permit verification of large designs. In addition, the latest release features support for measurements, enhanced partitioning algorithms, and fast simulation on a number of circuit topologies. ATS is an accelerated, transistor-level, time-domain simulator specifically developed for very large, custom digital and mixed-signal circuits. It combines the speed of metal oxide silicon (MOS) timing simulation with the accuracy of analog simulation provided by simulation program with integrated circuit emphasis (SPICE) simulators. Itýs integrated with Cadence Verilog and high-speed integrated circuit hardware description language (VHDL) simulators. ATS integrated with Cadence analog design environment is available now. For the ATS, a one-year U.S. list price is $39,600 and it is available on UNIX-based workstations from Sun Microsystems and Hewlett-Packard. Cadence Design Systems, Inc. San Jose, CA. Contact www.cadence.com

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