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Tools and Technologies
- C-based system-level design tool Cocentric SystemC Compiler synthesizes and optimizes designs described in SystemC. It generates a gate-level netlist for IC implementation or a synthesizable RTL description in VHDL or Verilog. The tool was designed to be the bridge between system designers who create algorithms, model designs, and verify SOC designs in C/C++, and hardware designers who implement those designs in silicon. Designers can use SystemC datatypes and language constructs to refine the original C/C++ code into a form acceptable as input for synthesis. The resulting SystemC hardware description can then be verified with the original C/C++ testbenches, ensuring compliance with the system specification. Using the tool, designers can synthesize the verified SystemC hardware description directly into a gate-level netlist or into a synthesizable VHDL or Verilog RTL description. The tool is integrated with the Synopsys' synthesis infrastructure. SystemC Compiler shares its timing engine and synthesis libraries with the company's Design Compiler. Verilog and VHDL modules, such as already existing IP reuse blocks, can be combined with the output of SystemC Compiler in a Design Compiler flow. Cocentric SystemC Compiler is available now and per copy pricing starts at $ 40,000 for a perpetual term license. Contact Synopsys, Inc. Moutanin View, CA www.synopsys.com
- Electrical rule checker Arctic can be used to check the electrical integrity of complex digital, memory, and mixed analog-digital circuits. The tool allows designers to translate their own knowledge base into a programmable set of rules, and to check a design for rules violations. The tool is a static rule checker that can be used to check SOC designs against electrical rules. The rules include both built-in checks and user written rules. The built-in checks include checks for issues related to circuit topology (incorrect transistor sizing), timing (latch writability), and noise immunity (charge sharing). User written rules can include design methodology checks plus additional electrical checks that are pertinent to the circuit design style being used. The tool requires a SPICE netlist and a control file in Tcl format. Arctic also accepts interconnect parasitics including coupling in DSPF and SPEF formats. It generates error reports in HTML format. Each failure can also be highlighted back on the schematic. Arctic is available now. Pricing starts at $17,000. Contact Cadmos Design Technology, Inc. San Jose, CA www.cadmos.com
- Parametric design rule checker VN-Check was designed to boost confidence in the quality of Verilog and VHDL integrated circuit (IC) designs early in the chip development cycle, to help identify design bugs as early as possible, and to facilitate the reuse of existing designs. The tool is part of the Verification Navigator design verification environment, which also provides code coverage, test suite optimization, state machine coverage, and circuit activity analysis. VN-Check utilizes Verification Navigator's graphical user interface (GUI), enabling designers to navigate through large amounts of data quickly. It also provides batch-mode textual reports to simplify integration into back-end flows. With VN-Check, designers have access to a set of more than 400 built-in design rules for both Verilog and VHDL. The built-in rules include specific checks for synthesis and simulation, coding style, documentation, and naming conventions.
Its design rules are parameterized, enabling rule behavior to be adjusted as needed by individual users or corporate CAD groups. Rule parameters can be used to control everything from clock type checks to the maximum number of items in a case statement.
In addition, actions taken when rule violations are detected can be customized for each rule with three levels of severity and custom messages. The tool also offers an application programming interface (API) and custom rule generator to implement complex new rules for VN-Check. Rules are specified using Java. VN-Check for Verilog is available now. List price for VN-Check starts at $15,000 for a single language when bundled with the base configuration of Verification Navigator. Contact TransEDA Los Gatos, CA www.transeda.com
- Logic abstracter tool Transistor Logic Abstracter (TLA) abstracts logic-level Verilog functional models from Spice or Spectre transistor-level netlists. The tool was designed to make possible the use of high-performance, logic-level verification methods such as gate-level simulation, emulation, and formal equivalence checking. The tool uses analytical techniques to determine the functionality of a custom block. These analytical techniques ensure that TLA's output is functionally correct, and enable it to handle both combinational and sequential circuits implemented in any of the common digital MOS design styles, including static CMOS, ratioed logic, precharge/domino logic, pass-transistor logic, and Cascode Voltage Switch Logic (CVSL). Abstraction removes the details of the specific implementation style while preserving the logical functionality, so the resulting abstracted functional model simulates much faster and can be compared with an abstract RTL specification through formal equivalence checking. In addition to event-driven simulation and equivalence checking, the abstracted models are also suitable for cycle-simulation and emulation. The Transistor Logic Abstracter is available for UNIX-based workstations from Sun Microsystems and Hewlett-Packard. The U.S. list price starts at $72,000. Contact Cadence Design Systems, Inc. San Jose, CA www.cadence.com
- C++ hardware-design class library Cynlib 1.2 is the latest version of the open-source EDA C++ hardware-design class library. Cynlib 1.2 has been enhanced to make it compatible with a variety of EDA tools from leading vendors. Added features include support for VSIA data types, tri-state signals for modeling buses, Cynlib API which enables the integration of the Cynlib simulator into existing tools, and expanded design libraries that enable the quick representation of flops and other low-level primitives. Users will also have the option of adding a Verilog co-simulation interface that enables Cynlib to co-simulate along with a
- Verilog or VHDL simulator. The tool contains an API which implements the standard functions required for a C++/Cynlib model to be treated as a simulation model by other design tools. Patterned after the Verilog PLI, the Cynlib API provides the required functionality for tools that work with Verilog to work smoothly with C++/Cynlib. Cynlib 1.2 is freely available under an Open-Source license and can be downloaded directly from the Cynapps website. The Verilog Co-Simulation Interface is available as an add-on to Cynlib and is priced at $25,000 for five licenses. Contact Cynapps, Inc. Santa Clara, CA www.cynapps.com
- Memory subsystem generator Databahn is an online tool for memory subsystem generation. Databahn generates synthesizable memory controller cores for the latest memory architectures, and automatically produces C- level verification support for the memory controller and associated memory. Designers can go online to select a set of memory components, specify a memory controller configuration, and then receive synthesizable RTL code for the controller and C-level simulation models for the resulting memory subsystem. The tool targets memory technologies such as SDRAM, FCRAM, and DDR-SDRAM, with plans to add support for other technologies later. One feature of the tool is its ability to automatically generate C models for high-level architectural analysis and verification. The same models are used for functional verification, where they are tightly integrated to leading EDA tools including: VHDL and Verilog simulators, testbench generators, hardware-software co-verification, and system-level design tools. Databahn is available immediately at a base price of $150,000. Contact Denali Software, Inc. Palo Alto, CA www.denalisoft.com
- Test program generation tool TDS Wavebridge module for the Credence Quartet series of mixed-signal test systems enables engineers to create digital test patterns and timing data from simulation and automatic test pattern generation (ATPG) files.
Credence will also ship complimentary copies of Fluence's Testbenchplus with each order of a Credence Quartet test system. The TDS Credence Quartet-100 WaveBridge is priced at $39,000 and is available now. Contact Fluence Technology Beaverton, OR www.fluence.com
- Enhanced ASICs The configurable RAM block is the third enhancement in seven months to the 0.35 micron XL Array ASIC and standard cell families. Each block in the XL Array ASIC family supports 4K bits of 2R-2W dual-port RAM. For maximum design flexibility, each port's dimension can be individually configured. Ports can be turned off completely to conserve power. Smaller dual port or single-port configurations are also possible. Like the advanced FPGAs, the AMI embedded RAM block may be configured in different dimensions. In addition, each port can be configured with a different dimension. This drop-in replacement design is intended primarily for a full range of synchronous applications, from interprocessor communication and increasing memory bandwidth through elastic storage for telecom buffers or network packet switching. Enhanced XL Array ASICs are available now with the new configurable RAM block that matches all commercially available FPGAs. Pricing starts at $2.00 each for 100,000 unit quantities per year in a 100-pin PQFP. American Microsystems, Inc. Pocatello, ID www.amis.com
- IC design chain portal Siliconx.com is a business-to-business (B2B) portal which aims to help designers locate, identify, select and engage with a variety of IC design and manufacturing solutions, through its Resource Locator and Silicon Services Mall. Services include design services, Intellectual Property (IP), libraries, electronic design automation (EDA) tools, wafer fabrication, packaging and assembly, test services and equipment. Siliconx.com was designed to be a resource for engineers and managers responsible for new semiconductor product design, manufacturing, and production. The portal features the Resource Locator, which includes a domain specific search engine coupled with a vendor capabilities database. Users can specify the type of service or product they need, desired attributes, and launch the search process. The search engine scans the vendor capabilities database and produces a list of vendors that meet the desired criteria. After examining the results, users can use the request for information (RFI) tool, and engage with selected vendors. The site also includes the Silicon Services Mall, which offers a dedicated presence for Silicon Partner Program Members. Using the Design Chain Management infrastructure, member companies offer design information, tools, and services. Contact Siliconx San Jose, CA www.siliconx.com
- Compute Farm The Sun Technical Compute Farm was designed to address the skyrocketing demand for increased computing power for customers in electronic design automation (EDA), computer-aided engineering (CAE), bioinformatics, simulation, and other compute-intensive industries. Sun TCF is a complete, rack-based compute farm that integrates Sun's enterprise servers, computing engines, and storage arrays, as well as networking equipment and resource management software. SunTCF is available now. Pricing starts at $270K. Contact Sun Microsystems Palo Alto, CA www.sun.com
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