The semiconductor, EDA, and IP communities are constantly developing new technologies, tools, and products to help designers manage the increasing complexity. Higher levels of abstraction and, in particular, the significant reuse of proven IP blocks contribute considerably to the battle against complexity. The constantly improving underlying silicon performance is allowing designers to use some of the ýspareý performance solely to help manage complexity. This effort shows up in many aspects of IC design technology, including standard cell libraries, high-level design languages, and reusable IP blocks. In a world where time-to-market can be much more critical than pure performance, using a little of the performance to help reduce design complexity is an important characteristic of many IC design advances.

As we move to block-based IC design, the fight with complexity takes on a new front: managing the interfaces between all the different blocks. Here again, help comes from advances such as the adoption of standard on-chip buses (today, largely based on embedded processors), while the presence of sufficient underlying silicon performance often allows the simplification of the system partitioning. Once again the key ally in the fight to manage complexity is the continually increasing silicon performance.

In one critical area, however, some of the technology trends havenýt been so encouragingýspecifically embedded memory. As we enter the era of system-level integration, IC designs require more and more embedded memory, already the single most pervasive IP block that IC designers use. Indeed, the very fact that embedded memory is accounting for a larger and larger percentage of IC chip area has resulted in tremendous pressure to reduce the area cost of these very large blocks. The use or planned use of DRAM technology for embedded memory has been a direct response to this increasing need for lower-cost embedded memory. The single-transistor cell used by DRAM allows the economical integration of much more embedded memory than traditional six-transistor-based SRAM has allowed. This innovation is helping drive integration towards the system-on-chip level required to meet the size, power, performance, and cost demands of key applications.

Unfortunately, in the fight to manage design complexity, the use of DRAM rather than SRAM doesnýt represent a move forward. The underlying reason is the poor random access cycle performance of traditional DRAM compared to SRAM. Forced to contend with random access cycle performance an order of magnitude lower than SRAMýrather than being able to use ýspareý raw performance to manage complexityýdesigners using embedded DRAM must add complexity just to overcome the lack of memory performance. This consequence appears in many designs where the embedded DRAM ýmemory controllerý consumes tens of thousands of gates and often includes FIFOs or cache SRAMs to mask some of the DRAM performance deficiencies. The challenge for foundries and ASIC vendors is to offer system-level IC designers high-density embedded memory that performs well enough to relieve them of the need to add complexity to overcome the low performance of these large memory blocks. When evaluating embedded memory technologies, designers of system-level ICs need not only to look at the density of the memory technology itself, but also at how much chip area and design time it will take to buffer the application from the memory, not to mention braving the risks associated with that interface design. Again, raw underlying performance can serve to simplify interfaces and help manage the overall design complexity.