As design teams take advantage of emerging semiconductor process technologies, the pressure intensifies to extend the design cycle for today's complex devices, which in turn negatively impacts time-to-market obligations.

Functional design and verification within system-on-a-chip (SOC) methodology provides the principal motivation for design-time extension. While 0.25-ým and 0.18-ým processes enable complete systems to be squeezed onto a single chip, problems with functional design and verification have reached crisis proportions. Clearly, a new SOC design methodology is needed, and fast.

A spate of software and techniques has been introduced over the last several years to try to address the problem. In many cases, however, the solutions have exacerbated the problem.

To add to the confusion, a plethora of new design language proposals has been offered up to the electronics industry since the middle of 1999. Several of the proposals suggest tailoring existing programming languages — for instance, C/C++ or Java — to provide the answer. Many feel that C/C++ and Java, created to meet altogether different programming needs, would most certainly introduce new problems not readily apparent prior to implementation in real IC design scenarios.

Hence, getting the methodology back on track requires a brand new design language that must offer three essential elements — Unification, Speed, and Evolution — otherwise known as the USE metric.

Clearly, the most critical aspect of the USE metric is unification of the design flow. The multitude of tools, languages, and techniques currently required, each solving a specific design problem, awkwardly lay on top of underlying IC design flows. As well as being difficult to maintain, the design flow has become hard to use, hard to learn, and suffers from tool performance problems.

A new language must, therefore, incorporate the needs of the entire SOC design flow, unifying architectural specification, system partitioning, performance analysis, test specification, software planning, hardware implementation, software design, and functional test application. No small task.

The second part of the USE metric provides improved design speed: A new language should dramatically shrink design cycle times in a number of ways. It should leverage greater design abstraction, utilize efficient constructs to aid coding and debug power, and eliminate slow tool interfaces by providing a single source for design needs. The language must also enable new technologies such as model checking and behavioral synthesis. Designers need to start using such a language quickly — efficiently building and debugging components and utilizing up-to-date design techniques.

Finally, the language should provide an evolutionary path from existing methodologies to the new language. No project team can spend four to six weeks learning a new methodology. They need the ability to use their current modeling styles and techniques and, over time, bring in the new constructs as required. A new language must be able to evolve from current techniques.

Current C/C++ and Java proposals aren't USE-able. C/C++ and Java, even with suggested modifications and/or library extensions, don't allow VHDL and Verilog hardware description language designs to evolve. Nor do they enable cross-design flow utilization. Other proposals, which suggest using test utilities, system languages, and extensions, only address part of the problem and are orthogonal to design flow unification.

Applying the USE-ability requirements, Co-design Automation, in conjunction with partners, customers, and industry experts, has developed a new design language called Superlog. It was developed to improve the efficiency and speed of the SOC design flow. Superlog represents an evolutionary step from Verilog HDL and utilizes powerful, C-based constructs for system design and decomposition, while providing an elegant and natural coding style.

SOC design requires new thinking if the creation of complex devices is to be accomplished. It is essential that a new design language be USE-able and provide methodology unification, design cycle speed, and use-model evolution if project teams are to get the most out of the available silicon area.

Simon Davidmann in CEO of Co-Design Automation Inc. (San Jose, CA). He has 18 years of EDA industry experience and, most recently, ran Ambit Design Systems' European office.