Currently, ultra deep submicron (UDSM) IC designs are breaking the traditional synthesis-place and route flow. Engineers experience this problem as iteration, iteration, and more iteration, at the back end of the design process. Who's to blame: synthesis or physical design? Maybe both.

Synthesized timing constraints along critical paths are layered on physical placement and routing, but the nature of these paths changes with physical placement choices. The wire-load view from synthesis is inaccurate, causing the synthesized netlist to be oversized in some places and undersized in others. Designers don't see the impact of this until they extract the interconnect parasitics, abstract them back to SDF format with a delay calculator, and run them again in their favorite timing tool.

Why the timing mismatch? Timing closure means you must match the drive strengths to the real loads, which are functions of the physical placement choices. The components of static timing in a design are the wire resistance-capacitance (RC), the intrinsic gate delay, and the gate delay from signal loading. In a perfect design, the wire RC would always be zero and the intrinsic gate-delay remains constant. Compared to logic restructuring techniques, which can yield a five-seven percent improvement in timing, there is a much greater opportunity for improvement in optimizing the wire-delay and gate-delay from loading. However, to accomplish this, the optimization tool must understand the electrical view of the design as placement of blocks and cells changes dynamically during optimization.

Making timing expectations based on synthesis-derived wire estimates without the real physical placement is highly improbable. To meet a design with 7.5ns (133MHz) clock period they target the timing-driven flow at 6.0ns (166MHz), use slow corner libraries for design, make pre-emptive transition time fixes for all signals, and use higher capacitance and resistance coefficients. Then they go through multiple iterations of hand editing netlists and making last minute ECOs to make it all work. Sound familiar?

Enter in-place optimization (IPO) methods and floorplanning tools. Iterative methods like IPO result in excessive buffer insertion, nearly 10 times the number of buffers really needed. Budgeting solutions like floorplanning eat away valuable time in the clock cycle. Results from both solutions fall to the lowest common denominator, meeting timing closure, but at the price of low performance and increased area.

Today, designers must spend more dollars retooling to address timing closure because none of the timing-driven approaches really work. Synthesis-and-placement solutions and new layered software are now being offered in addition to the traditional tools. Do you throw away synthesis? Place and route? The whole flow? This is not an easy decision. What good is a timing guarantee if you fail to meet market requirements due to poor product performance or excessive cost?

Merging and layering might have worked if system-on-a-chip (SOC), intellectual property, and increased performance expectations hadn't entered the design picture. Now design objectives take on a systems-level flavor. Real SOC design closure requires designs to meet electrical requirements such as noise margins, reliability requirements, and power constraints in addition to timing. You need to create such a design view because it doesn't exist in either the logical (synthesis) or physical (place-and-route) tools.

Placement in synthesis and re-synthesis during placement are both emerging, as solutions and good results are possible. But look carefully at the difference between placement awareness and explicit placement, between noise and power awareness and explicit noise and power analysis. The quality of results will suffer if the focus of timing closure isn't expanded to real design convergence.

To ensure UDSM design convergence, you must analyze, place, and optimize designs in the timing, signal integrity, and power dimensions simultaneously. The process must be both interactive and incremental and maintain a persistent view of how the design is changing electrically. Optimization early in the design process provides an elegant "fix" to the problem of endless back-end iterations while also delivering the necessary quality assurance for noise and power issues.