Thankfully, it's becoming increasingly common for design for testability (DFT) issues to be addressed at design reviews prior to circuit tape-out approval. Previously, in the age of schematics, this often required design and test engineers to pore over mounds of pages looking for things like asynchronous set/reset circuit configurations, derived or internally generated clocks, and combinational and sequential feedback loops. The review inevitably occurred late in the design cycle, adversely affecting project schedules if glitches were found, and making for an uncomfortable process for the circuit designer. With today's design practices, however, schematics are mostly a thing of the past. But finding DFT problems in language-based designs is still not a simple task for humans.

Designers can take more control of the DFT review - before anyone else sees their designs - by performing DFT rule checking at the RTL (Verilog or VHDL) level.

Like "lint" tools, RTL DFT tools can be used to find the majority of common testability problems prior to logic synthesis. That is, if their bosses will approve the funds for the purchase of such tools.

The EDA market is estimated to be in excess of $3 billion. Of that, less than $100 million - about 3 percent - is attributable to DFT and built-in self-test (BIST) tools. At the same time, ATE costs are rising above the $5 million mark per unit level, and test development and execution costs are increasing to well over 35 percent of the overall design and production costs. This gap does not bode well for companies that want to ship high quality products in a timely manner.

The only solutions to lowering test costs with DFT - and increasing BIST effectiveness, particularly for embedded cores and memory blocks - lie in the hands of the circuit designers. They need tools to identify and correct any testability problems on their own as early in the design cycle as possible: tools that will automatically create RTL memory and logic BIST code that can be included in the synthesis process; tools that will automatically generate IEEE 1149.1 test access-port controllers and the necessary boundary scan description language file; tools to make designs scannable; and tools to find out just what kind of fault coverage the test benches and test strategies are achieving.

And herein lies the dichotomy. Most people view test as a "back end" issue. Phrases such as "We'll worry about test later - we've got time-to-market issues here!" and "Test is someone else's problem - I need to get more features in!" are commonly heard in design groups. But it doesn't matter how many features are allowed to creep into a design, how small the device geometries have shrunk, or how much the gate counts have increased if the design can not be adequately tested, the risk in shipping it remains very, very high.

My experience in teaching and preaching DFT and BIST for the last 25-plus years leads me to believe that designers do not intentionally make designs untestable. They've just never been educated about DFT and test issues. Even today, these topics are sparsely taught in universities and, even then, usually only at the graduate level.

So what's a circuit designer to do to avoid embarrassment at design review time? First, use an RTL DFT rule checker early - and frequently - as the Verilog or VHDL code comes together. Tools for this purpose today can find 90 percent or more of the possible testability problems, which lead to long automatic test pattern generation (ATPG) run times, high numbers of test vectors, and less-than-optimum fault coverage.

It's time to move testing concerns from the back end to the front end of the design cycle. That is where the real leverage occurs. It's time to insist that designs be checked just as carefully for testability as they are for path delays and conformance to functional specifications. It's time to invest in DFT and BIST tools that designers can use to prevent test problems, rather than spending a pittance for the test engineers who must try to overcome the difficulties embedded in a complex chip design.

Time to use the secret weapon!

Jon Turino is the director of marketing and business development for Syntest Technologies. Prior to Syntest, he held senior marketing and management positions with Integrated Measurement Systems and Mentor Graphics Corp. He is the author of three books and hundreds of papers on DFT and BIST. Mr. Turino founded the IEEE P1149 testability bus standardization committee, and was instrumental in the adoption of JTAG boundary scan and the mixed-signal testability bus standard.