Is it necessary to move beyond the register transfer level (RTL) of the electronics design cycle to solve the verification problem? Engineering organizations have invested heavily in resources and trained their designers to use the current RTL-based tools and associated methodology. It seems that there must be a way to solve the mighty verification problem without starting over or implementing solutions that solve only a piece of the problem. Has it occurred to anyone that we could revisit old solutions, apply new techniques, and save a methodological change for another time?

The electronics industry is talking seriously about moving beyond RTL. Some designers think this is necessary because simulation performance of detailed RTL causes a bottleneck. They add that it takes too long to verify RTL code because of exhaustive execution times and large test suites. Co-verification performance is not satisfactory, they claim. According to popular opinion,it takes too long to write RTL versus designing with a higher-level language code. Finally, electronic design automation (EDA) software companies may see this as an opportunity to sell new tools and design methodologies.

All this adds up to a mad dash toward a higher level of design abstraction. No one denies that design verification is a consuming resource in project schedules. Determining if a multi-million gate design will execute all of its functions with accurate results is daunting. Because of the interaction between a growing number of functional units within a design, the complexity of the functional verification problem grows faster than the growth in design density. To get products to market in a timely fashion, teams are forced to test less or find more effective ways to test. This is all caused by inefficiencies at the register-transfer level, say industry pundits.

Let's take a contrarian view for now. Why should electronics designers move beyond RTL? I say they shouldn't. Behavioral synthesis still only works for niche architectures, so designers still have to write RTL code. Accurate performance analysis requires cycle modeling. From what I've seen, current design language proposals are more like libraries and functions to make C/C++ work and look like the Verilog hardware description language (HDL). I would say the industry isn't ready to move.

Let's look instead at devising a better RTL-based solution, using the best approaches from both the hardware and software domains and optimizing them. The approach would create an efficient link between the domains and, most importantly, focus on fixing the design verification bottleneck.

What am I talking about? Here is one example: Hardware engineers frustrated with current verification solutions founded Tharas Systems. They found that software solutions ran out of steam on large designs, no matter how generously a workstation was configured. Hardware solutions were too hard to use, with huge compilation times, and expensive to purchase and maintain. These designers set out to create a technology that would yield the blend of performance, capacity, ease of use, and cost that is needed for chip designs. Their goal was to develop a cost-efficient, high-performance RTL accelerator. They recognized that they needed to integrate the interconnect and communication between a large number of specialized processors.

Previous attempts have used bus architectures that suffered from resource conflict and algorithmically intractable scheduling problems. Other approaches have pushed the interconnect problem off to field programmable gate array (FPGA) routing resources, a solution requiring place and route for every simulation, and ensuring long compile times and high costs.

As you might expect, I believe a reasonable solution is a combination of hardware and software. The software would provide a seamless link to the existing test and verification practices and tools, while the hardware would deliver flexible performance and capacity characteristics.

Design verification is in desperate need of a breakthrough. New EDA hardware and software suppliers are offering innovative approaches to the design verification problem that may just offer the solution by applying new techniques to old solutions. Let's look here instead of at an entirely new methodology.

Steve Carlson is CEO at Tharas Systems (Santa Clara, CA), a startup providing hardware acceleration technology. He has worked in the high-tech area since 1983 for LSI Logic, Synopsys, and UTMC.