Effective Design Verification
			by Larry Saunders Testbench suites aid in the implementation of verification plans.
		Simulations Mixed-Signal Tests to Reduce Time-to-Market
			by Nash Khouzam A virtual tester paves the way for the real thing.
		FPGAs Shrink With Physical Design Reuse
			by John Mahoney Time-to-market requires fast and accurate design migration to new processes.
		Focus Report: HDL Add-In Tools
			by R.T. "Tets" Maniwa A quick survey of the "other" tools that make the design, verification, and synthesis jobs easier for the designer.
		Editorial
			by Jonah McLeod Design-Tool Evolution About to Enter a New Cycle
		Viewpoint
			by Daniel Chapiro The Next Frontier: High-Level Functional Verification
		In The News
		Tools & Technologies