IP Design Flow Centers on Automatic HDL Translation
			by Jake Karrfalt and Thomas Oberthür Designers at SICAN devloped a new ASIC design flow that automatically translates VHDL into Verilog, producing intellectual property available in both languages.
		The New RTL Analysis Methodology
			by Steven E. Schulz Meeting the challenges of very deep submicron design requires a new approach--the RTL virtual prototype.
		Automating the Design Flow from System to Gates
			by Dean Kawaguchi and Sarosh Vesuna Facing the most complex ASIC design in the company's history, Symbol Technologies used behavioral-level design tools to successfully complete a DSP-based wireless LAN solution.
		Hardware Emulation Accelerates HDL Functional Verification
			by Tom Balph and Wilson Li Very large evaluation suites require more cycles than simulators can provide.
		Focus Report: Electronic System-Level Design Tools
			by Gil Bassak Abstract representations aid designers pressed between complex circuits and tight schedules.
		Editorial
			by Jonah McLeod Why Most Engineers Insist on Unix
		Viewpoint
			by Surrendra Dudani Code Coverage: 'Go with the Flow'
		In The News
		Tools & Technologies