Using Clock Skew as a Tool to Achieve Optimal Timing
			by Joe G. Xi and David Staepelaere High-performance designs may call for a nonzero clock skew for robust clocking schemes. Employing nonzero skew can help increase performance as well as extended a chip's safety margins.
		Automating Functional Design Verification
			by Allen Harris and Derek Pappas Sun creates a flexible, reusable multi-ASIC and system verification environment with a single engineer and proves its worth on a workstation graphics subsystem.
		Taking a Graphical Approach to Programmable Logic Design
			by Ken Frick and Eric A. Bumbera Designers of programmable logic devices can make the transistion from schematics to HDL relatively painless by migrating to a graphical design capture tool.
		Truth Table Models for EDA Tools
			by Greg Haynes The guidelines here can help ASIC library modelers create a consistent truth table style for commonly used EDA tols that minimizes debugging problems and aids the automated creation or translation of the tables.
		Focus Report: ASICs and Foundries
			by Gil Bassak With CMOS IC features plummeting to 0.18ým and below, foundries as well as ASIC vendors are seeking ways to help narror the design gap.
		EDA Takes Advantage of an NT Compute Farm
			by Wendy Stresau and Ben Buzonas Compaq is migrating to a Windows NT-based EDA environment. The first step, building an NT compute farm using its own machines and several carefully selected support applications, is paying off.
		Editorial
			by Tets Maniwa Got VDSM? Cooperate!
		Viewpoint
			by John Perry Take the High(-Level) Road to Fast Verification of Complex ASICs
		In The News