Bringing High Availability to the Masses By Fred Rehhauser A standards-based approach makes high availability much more realistic.

Designing ADSL Chip Sets for Rapid Integration By Bernard Goffart The history and subsequent design of a mixed-signal chip set presents interesting comments - especially given its first pass fab success. Formal Verification of an MPEG Decoder Chip By Avi Parash The industrial use of formal verifiaction methods provides a crucial assist in designing an MPEG decoder chip. Hierarchal Physical Design for Megagate ASICs By Sam Appleton Raw design size in megagate ASICs can cripple physical design and timing closure - physical hierarchy is the solution. Focus Report: Timing Analysis By Steven E. Schulz

Editorial By Peggy Aycinena The Power of the Pen Inside EDA By Tets Maniwa What Happened at DAC? Viewpoint By Jon Turino RTL DFT Rule Checking - The Circuit Designer's Secret Weapon

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