ASIC Design Flow Scores on First Pass
			by Shekhar Patkar and Pran Kurup Engineers at Crystal Seminconductor and Cirrus Logic team up to design a wavetable synthesizer chip
		Creating a Cost-Effective Alternate Supply for Single-Sourced ICs
			by George Chamberlain, Larry Lam, and Les Thurlow Component supply interruption? Here's a way to minimize costly board redesign and time-consuming system requalification.
		Using Hierarchical Clock Tree Synthesis to Generate Balanced Clock Trees
			by Pierre Ragon and Abhijeet Dugar High-performance ASICs require careful clock design to achieve full performance from ASIC processes.
		The Seven Deadly Sins of Scan-Based Designs
			by Benson Cheung and L.T. Wang This article may be your DFT salvation. Scan-based design in ASICs requires attention to certain design techniques.
		Focus Report: Design Libraries
			by R.T. "Tets" Maniwa The building blocks for all ASIC designs start with the libraries.
		Editorial
			by Jonah McLeod Spending the Evening with "ALF"
		Viewpoint
			by Amr Mohsen Reconfigurable System Prototyping: A Fast Solution for Functional Verification
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		Tools & Technologies