Reconfigurable Logic Modeling
			by Kevin Dwiat and Warren Debany Using an HDL for FPGAs improves designer productivity.
		Focus Report: Programmable Logic
			by Larry Waller High-density PLDs grab the spotlight as vendors go after gate array "sweet spot."
		Special Section: CHDS--Next Paradigm for Deep Submicron EDA?
			by Steven E. Schulz Steve tells us how the SEMATECH member companies are addressing the "design gap."
		SPY vs. SPY: the VMC Story
			by John Cooley How a past Cadence monopoly helped boost Synopsys and Viewlogic in today's IP market.
		Editorial
			by Jonah McLeod Managing 100 kgate Designs Demands a New Design Methodolgy
		EDA Platform
			by Steve E. Schulz IP in HDL Using EDA for IC
		Viewpoint
			by Dennis Ray Harmon EEs Need IT for EDA
		In The News
		Tools & Technologies